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MC56F8025VLD Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MC56F8025VLD Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 160 page 56F8025 Data Sheet, Rev. 3 Freescale Semiconductor 3 Preliminary 56F8025 Block Diagram Programmable Interval Timer Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller 4 Unified Data / Program RAM 2K x 16 PDB PDB XAB1 XAB2 XDB2 CDBR QSPI or PWM or I2C or TMRA or GPIOB IPBus Bridge (IPBB) System Bus Control R/W Control Memory PAB PAB CDBW CDBR CDBW JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg Low-Voltage Supervisor VCAP VDD VSS VDDA VSSA 4 RESET or GPIOA AD0 4 Clock Generator* System Integration Module P O R O S C PWM or TMRA or CMP or GPIOA *Includes On-Chip Relaxation Oscillator COP/ Watchdog AD1 4 Program Memory 16K x 16 Flash ADC or CMP or GPIOC QSCI or PWM or I2C or TMRA or GPIOB 3 3 I2C or CMP or GPIOB 2 2 XTAL, CLKIN, or GPIOD EXTAL or GPIOD 2 11 DAC • Up to 32 MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 32KB (16K x 16) Program Flash • 4KB (2K x 16) Unified Data/Program RAM • One 6-channel PWM module • Two 4-channel 12-bit Analog-to-Digital Converters (ADCs) • Two Internal 12-bit Digital-to-Analog Converters (DACs) • Two Analog Comparators • Three Programmable Interval Timers (PITs) • One Queued Serial Communication Interface (QSCI) with LIN slave functionality • One Queued Serial Peripheral Interfaces (QSPI) • One 16-bit Quad Timer • One Inter-Integrated Circuit (I2C) port • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 35 GPIO lines • 44-pin LQFP Package 56F8025 General Description |
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