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MC56F8347VPYE Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC56F8347VPYE Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 172 page  Architecture Block Diagram 56F8347 Technical Data, Rev.11 Freescale Semiconductor 11 Preliminary Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. 56800E Program Flash Program RAM Data RAM EMI Data Flash IPBus Bridge Boot Flash Flash Memory Module CHIP TAP Controller TAP Linking Module NOT available on the 56F8147 device. JTAG / EOnCE pab[20:0} pdb_m[15:0} cdbw[31:0} cdbr_m[31:0} xdb2_m[15:0} xab2[23:0} xab1[23:0} Address Data Control 24 16 10 To Flash Control Logic External JTAG Port IPBus 5 |
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