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PR31500ABC Datasheet(PDF) 11 Page - NXP Semiconductors |
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PR31500ABC Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 24 page Philips Semiconductors Preliminary specification MIPS PR31500 Poseidon embedded processor 1996 Sep 24 11 PIN # NAME AND FUNCTION TYPE NAME UART and IR Pins 55 TXD O This pin is the UART transmit signal from the UARTA module. 54 RXD I This pin is the UART receive signal to the UARTA module. 59 IROUT O This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if Consumer IR mode is enabled. 58 IRIN I This pin is the UART receive signal to the UARTB module. RXPWR O This pin is the receiver power output control signal to the external communication IR analog circuitry. 62 CARDET I This pin is the carrier detect input signal from the external communication IR analog circuitry. Video Pins 91 FRAME O This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to return it’s pointers to the top of the display. The Video Module asserts FRAME after all the lines of the LCD have been shifted and transferred, producing a full frame of display. 93 DF O This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to toggle every programmable number of LOAD signals. 94 LOAD O This pin is the line synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to transfer the contents of it’s horizontal line shift register to the LCD panel for display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD. 95 CP O This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and sampled by the LCD on the falling edge of CP. 101, 100, 99, 98 VDAT(3:0) O These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD. 90 DISPON O This pin is the display-on enable signal for the LCD. Test Pins 74 TESTSIU I This pin allows external logic to initiate read or write transactions to PR31500 registers. The TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and /DGRNT), then external logic can initiate read and write transactions to PR31500 registers. This pin is used for debugging purposes only. 71 TESTCPU I This pin allows numerous internal CPU core signals to be brought to external PR31500 pins, in place of the normal signals assigned to these pins. The CPU core signals assigned to their respective pins during TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled by asserting this TESTCPU signal, and this function is provided for generating test vectors for the CPU core. This pin is used for debugging purposes only. 72 TESTIN I This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only. 73 VIDDONE O This signal is used to synchronize UCB1100 to read touchscreen input, when there is no video data shifted into LCD panel. Spare Pins NC4–1 No Connect These pins are reserved for future use and should be left unconnected. 34 – Reserved. 32, 31 – Reserved. Power Supply Pins VDD (34 each) +3.3V These pins are the power pins for PR31500 and should be connected to the digital +3.3V power supply VSTANDBY. VSS (34 each) GND These pins are the ground pins for PR31500 and should be connected to digital ground. NOTE: For some vendor-dependent implementations of PR31500, pin 131 may be used for a filter capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground). |
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