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MC68HC908JB16 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MC68HC908JB16 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 332 page MC68HC908JB16 — Rev. 1.1 Technical Data Freescale Semiconductor Table of Contents 7 Technical Data — MC68HC908JB16 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.6.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .34 1.6.2 Voltage Regulator Output Pin (VREG). . . . . . . . . . . . . . . . . .34 1.6.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35 1.6.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . . 35 1.6.6 CGM Power Supply Pins (VDDA, VSSA0, VSSA1) . . . . . . . . .36 1.6.7 CGM Voltage Regulator Out (VREGA0). . . . . . . . . . . . . . . . .36 1.6.8 CGM Voltage Regulator In (VREGA1) . . . . . . . . . . . . . . . . . .36 1.6.9 External Filter Capacitor Pins (CGMXFC1, CGMXFC2) . . . 36 1.6.10 CGM Clock Output Pins (CGMOUT1, CGMOUT2) . . . . . . . 36 1.6.11 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). . 36 1.6.12 Port C I/O Pins (PTC1/RxD, PTC0/TxD) . . . . . . . . . . . . . . . 37 1.6.13 Port D I/O Pins (PTD5–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.14 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/T2CH01, PTE1/T1CH01, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . 37 Section 2. Memory Map 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 |
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