UPC8158K datasheet(1/5 Pages) NEC

Part #	UPC8158K

Description	AGC/UP-CONVERTER WITH IQ MODULATOR

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Manufacturer	NEC [NEC]

Direct Link	http://www.nec.com/

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AGC/UP-CONVERTER

WITH IQ MODULATOR

UPC8158K

DESCRIPTION

The UPC8158K is a silicon microwave monolithic integrated

circuit designed as a quadrature modulator for digital mobile

communication systems. This MMIC consist of a 0.8 GHz to

1.5 GHz up-converter and 100 MHz to 300 MHz quadrature

modulator which are equipped with AGC and power save

functions. This configuration suits IF modulation systems and

is packaged in a 28-pin QFN suitable for high density

mounting. The chip is manufactured using NEC's 20 GHz fT

silicon bipolar process NESATTM III to realize low power

consumption. Consequently the UPC8158K can contribute to

make RF blocks smaller size, higher performance and lower

power consumption.

FEATURES

• SUPPLY VOLTAGE:

VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V

• BUILT-IN LPF:

Suppresses spurious multipled by TX local (LO1)

• AGC AMPLIFIER INSTALLED IN LOCAL PORT OF

UPCONVERTER:

GCR = 35 dB MIN. @ fout = 1.5 GHz

• EXCELLENT PERFORMANCE:

Padj = -65dBc TYP. @

∆f = ±50 KHz, EVM = 1.2 %rms TYP.

• EXTERNAL IF FILTER:

Can be applied between modulator output and

up converter input terminal

APLICATIONS

• Digital cellular phones

(PDC800M, PDC1.5G,TDMA1900 and so on)

• Wireless Communiaction Systems

(MMDS, Broadband wireless access)

California Eastern Laboratories

Note:

1. Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.

PART NUMBER

UPC8158K

PACKAGE OUTLINE

SYMBOLS

PARAMETERS AND CONDITIONS

UNITS

MIN

TYP

MAX

UP-CONVERTER + QUADRATURE MODULATOR TOTAL

ICC (TOTAL)

Total Circuit Current, No input signal

mA

23.7

28

37.6

ICC(PS) TOTAL

Total Circuit Current at Power Save Mode, VPS

≤ 0.5 V(low), No input signal

µA

0.3

10

PRFout1

Total Output Power 1, VAGC = 2.5 V

dBm

-15

-11.5

-8

PRFout2

Total Output Power 2, VAGC = 1.0 V

dBm

-56.5

-52

-46.5

LOL

LO Carrier Leak, fLOL = fLO1 + fLO2

dBc

-40

-30

ImR

Image Rejection (Side Band Leak)

dBc

-40

-30

IM3(I/Q)

I/Q 3rd Order Distortion

dBc

-50

-30

GCR

AGC Gain Control Range, VAGC = 2 V

→1 V

dB

35

40

EVM

Error Vector Magnitude, MOD Pattern PN9

%rms

1.2

3.0

Padj

Adjacent Channel Interference,

∆f = ±50KHz, MOD Pattern: PN9

dBc

-65

-60

Pout(8fLO1)

Spurious Suppression, fLO1

× 8, fLO1 × 8 (image)Note

dBc

-70

-65

TPS(Rise)

Power Save Rise Time, VPS(Low)

→ VPS(High)

µs2

5

TPS(Fall)

Power Save Fall Time, VPS(High)

→ VPS(Low)

µs2

5

ZI/Q

I/Q Input Impedance, Between pin I/Ib, Q/Qb

k

Ω

80

200

II/Q

I/Q Input Bias Current, Between pin I/Ib, Q/Qb

µA5

13

ZLO1

LO1 Input VSWR, fLO1 = 100 M to 300 MHz

-

1.5 :1

ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V)

123

4

5

67

8

22

21

20

19

18

17

16

15

14

13

12

11

10

9

23

24

25

26

27

28

Phase

Shifter

I/Q-Mix

Reg

LPF

AGC

Up-Mix

AGCcont

INTERNAL BLOCK DIAGRAM

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