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13191 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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13191 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
11 / 24 page MC13191 Technical Data, Rev. 1.5 Freescale Semiconductor 11 Figure 6. SPI Interface Although the SPI port is fully static, internal memory, timer, and interrupt arbiters require an internal clock (CLKcore) derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. 6.2.1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13191 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 6. Figure 7. SPI Single Burst Timing Diagram. SPI digital timing specifications are shown in Table 6. Shift Register Baud Rate Generator Shift Register Chip Enable (CE) RxD MISO TxD MOSI Sclk SPICLK MCU MC13191 CE 1 23 4 5 6 7 8 CE SPICLK T1 T2 T4 T0 SPI Burst Valid T5 T6 T3 Valid T7 MISO MOSI Valid |
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