MC33143

5

MOTOROLA ANALOG IC DEVICE DATA

Figure 2. Output Response Waveform

VPwr – 3.0 V

50%

2.0 V

VPwr

tdlh

tdhl

tSRf

tSRr

0 V

5.0 V

0 V

IN1–2

OUT1–2

PIN FUNCTION DESCRIPTION

Pin

Symbol

Description

1, 12

IN1, IN2

INput 1 and INput 2 (IN1 and IN2) respectively determine the state of the corresponding output drivers

(OUT1 and OUT2) under normal operating conditions. When an input is high, it’s corresponding output

is active ON, and when low is disabled OFF. IN1 and IN2 have internal active pull–downs which allow a

floating input pin to be conservatively interpreted as a logic low, turning Off the output. An unused input

should be connected to ground.

2

CEN

Chip Enable (CEN) input pin, when low, disables both outputs (OUT1 and OUT2) and places the device

in a “sleep mode” reducing the bias current required from VDD and VPwr. A falling edge of CEN causes

OUT1 and OUT2 to rapidly turn OFF. A falling edge of CEN should precede any VDD shutdown to allow

time OUT1 and OUT2 to be disabled. When CEN is low, INTerrupt (INT) and STATus 1 and 2 (STAT1–2)

will be tri–stated (high impedance). The CEN pin can also be used for power–on reset and under

voltage lockout to disable the outputs for power supply voltages less than 4.5 V. CEN is a dependent

input from the system microcontroller unit (MCU) or some other integrated circuit. It has an internal

pull–up resistor to VDD affording a floating pin to be interpreted as a logic high. Rpull–up is greater than

50 k

Ω. If used externally, this pin should be connected to VDD.

3, 10

STAT1. STAT2

The STATus pins (STAT1–2) respectively indicate the presence of faults on OUT1–2. STAT1–2 will be

logic high during normal operation. A logic low will occur whenever an Open Load, Short–to–Ground,

Short–to–Supply (Battery), Thermal Limit, or Overvoltage Shutdown fault condition is experienced on a

corresponding output. STAT1–2 are both active low digital drivers. A 10 k

Ω resistor between STAT1–2

and the system CPU may improve a Failure Mode Evaluation Analysis (FMEA) score if STAT1–2 are

externally shorted to VPwr. If unused, this pin should be left connected.

4, 9, 16,

21

VPwr

These pins are connected to the supply and provide load current to the DMOS outputs, are used

pumping the DMOS gates, and for Overvoltage shutdown detection of the DMOS. The DMOS outputs

will turn ON with 5.5 to 24 V applied to VPwr. VPwr is limited to –1.5 V for a maximum duration of

250 ms. A 10 nF de–coupling cap is recommended to be used from VPwr to Ground.

5, 6, 7, 8,

17, 18,

19, 20

Gnd

These eight pins constitute the circuits ground (Gnd) and also provide heatsinking for the DMOS output

transistors. Ground continuity is required for the outputs2 to turn ON.

11

VDD

This pin is to be connected to the 5.0 V logic supply of the system. A 10 nF de–coupling capacitor is

recommended from VDD to Gnd.

13, 24

OUT1, OUT2

These pins are connected internally to the DMOS output transistors which source current into the

corresponding load. Each output incorporates dynamic clamping to accommodate inductive loads. In

addition, each output has independent short to ground detection and protection, current limit detection

and protection, thermal limit detection and protection, ON open load and or short to supply (battery)

detection. Neither output will turn ON if CEN is logic low. An unused output should be connected to a

10 k

Ω load to prevent false fault reporting. A 1.0 nF filter capacitor may be used from OUT to Gnd to

provide dV/dt noise filtering.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com