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MH32S64APHB-7 Datasheet(PDF) 8 Page - Mitsubishi Electric Semiconductor |
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MH32S64APHB-7 Datasheet(HTML) 8 Page - Mitsubishi Electric Semiconductor |
8 / 55 page MH32S64APHB -6,-7,-8 2,147,483,648-BIT (33,554,432 - WORD BY 64-BIT)Synchronous DRAM MITSUBISHI LSIs ( / 55 ) MITSUBISHI ELECTRIC 17.Mar.2000 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0379-0.1 COMMAND TRUTH TABLE COMMAND MNEMONIC CKE n-1 CKE n /S /RAS /CAS /WE BA0,1 A10 A0-9 Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Adress Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Bank PREA H X L L H L X H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto- Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TERM H X L H H L X X X Mode Register Set MRS H X L L L L L L V*1 H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address 8 A11 X X V X X V V V V X X X X X L |
Similar Part No. - MH32S64APHB-7 |
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Similar Description - MH32S64APHB-7 |
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