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TMS370C302AFNL Datasheet(PDF) 11 Page - Texas Instruments |
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TMS370C302AFNL Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 50 page  TMS370Cx0x 8-BIT MICROCONTROLLER SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 system reset (continued) Table 6. Reset Sources REGISTER ADDRESS PF BIT NO. CONTROL BIT SOURCE OF RESET SCCR0 1010h P010 7 COLD START Cold (power-up) SCCR0 1010h P010 4 OSC FLT FLAG Oscillator out of range T1CTL2 104Ah P04A 5 WD OVRFL INT FLAG Watchdog timer timeout Once a reset is activated, the following sequence of events occurs: 1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state). 2. Registers A and B are initialized to 00h (no other RAM is changed). 3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL. 4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH. 5. Program execution begins with an opcode fetch from the address pointed to the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. |
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