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33926 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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33926 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 24 page  Analog Integrated Circuit Device Data Freescale Semiconductor 11 33926 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make the 33926 a very attractive, cost- effective solution for controlling a broad range of small DC motors. The 33926 outputs are capable of supporting peak DC load currents of up to 5.0 A from a 28 VPWR source. An internal charge pump and gate drive circuitry are provided that can support external PWM frequencies up to 20 kHz. The 33926 has an analog feedback (current mirror) output pin (the FB pin) that provides a constant-current source ratioed to the active high-side MOSFETs’ current. This can be used to provide “real time” monitoring of output current to facilitate closed-loop operation for motor speed/torque control, or for the detection of open load conditions. Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. An input invert, INV, changes IN1 and IN2 to LOW = true logic. Two different output slew rates are selectable via the SLEW input. Two independent disable inputs, D1 and D2, provide the means to force the H-Bridge outputs to a high impedance state (all H- Bridge switches OFF). An EN pin controls an enable function that allows the IC to be placed in a power-conserving Sleep mode. The 33926 has Output Current Limiting (via Constant OFF-Time PWM Current Regulation), Output Short-Circuit Detection with Latch-OFF, and Overtemperature Detection with Latch-OFF. Once the device is latched-OFF due to a fault condition, either of the Disable inputs (D1 or D2), VPWR, or EN must be “toggled” to clear the status flag. Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering. The current limiting scheme is unique in that it incorporates a junction temperature- dependent current limit threshold. This means that the current limit threshold is “reduced to around 4.2 A” as the junction temperature increases above 160°C. When the temperature is above 175°C, overtemperature shutdown (latch-OFF) will occur. This combination of features allows the device to continue operating for short periods of time (<30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER GROUND AND ANALOG GROUND (PGND AND AGND) The power and analog ground pins should be connected together with a very low impedance connection. POSITIVE POWER SUPPLY (VPWR) VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces, offering as low impedance as possible between pins. STATUS FLAG (SF) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pullup resistor to VDD. The maximum VDD is <7.0 V. Refer to Table 5, Truth Table, page 14 for the SF Output status definition. INPUT INVERT (INV) The Input Invert Control pin sets IN1 and IN2 to LOW = TRUE. This is a Schmitt trigger input with ~80 µA sink; the default condition is non-inverted. If IN1 and IN2 are set so that the current is being commanded to flow through the load attached between OUT1 and OUT2, changing the logic level at INV will have the effect of reversing the direction of current commanded. Thus, the INV input may be used as a “forward/ reverse” command input. If both IN1 and IN2 are the same logic level, then changing the logic level at INV will have the effect of changing the bridge’s output from freewheeling high to freewheeling low or vice versa. SLEW RATE (SLEW) The SLEW pin is the logic input that selects fast or slow slew rate. Schmitt trigger input with ~80 µA sink so the default condition is SLOW. When SLEW is set to SLOW, PWM-ing should be limited to frequencies less than 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side MOSFETs. INPUT 1,2 AND DISABLE INPUT 1,2 (IN1, IN2, AND D1, D2) These pins are input control pins used to control the outputs. These pins are 3.0 V/5.0 V CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 3, Static Electrical Characteristics, page 6. |
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