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MPC859P/859T/859DSL PowerQUICC™ FamilyTechnical Summary

MOTOROLA

Embedded MPC8xx Core

Embedded MPC8xx Core

The MPC859P/859T/859DSL Family is comprised of three modules that each use the 32-bit internal bus:

the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The

MPC859P/859T/859DSL block diagram is shown in Figure 1.

Figure 1. MPC859P/859T/859DSLBlock Diagram

1.2

Embedded MPC8xx Core

The MPC859P/859T/859DSL Family integrates an embedded MPC8xx core with high-performance,

low-power peripherals to extend the Motorola data communications family of embedded processors farther

into high-end communications and networking products.

The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC architecture.

It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store operations in

hardware. The core supports integer operations on a 32-bit internal data path and 32-bit arithmetic hardware.

The core interface to the internal and external buses is 32 bits.

Bus

System Interface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

4

Timers

Interrupt

Controllers

8-Kbyte

Dual-Port RAM

10 Virtual

Serial 2

and

2

Independent

DMA

Channels

System Functions

PCMCIA-ATA Interface

4-Kbyte 1

Instruction Cache

32-Entry ITLB

Instruction MMU

4-Kbyte 1

Data Cache

32-Entry DTLB

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

4 Baud Rate

Generators

Parallel Interface Port

and UTOPIA

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Controller

and Program

ROM

SCC1

Serial Interface

I2C

SPI

SMC2 2

SMC1

Time Slot Assigner

MPC8xx

Processor

Core

DMAs

FIFOs

10/100

MII

Base-T

Media Access

Serial Interface

I2C

SPI

Time Slot Assigner*

Control

Fast Ethernet

Controller

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com