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MPC5553MVZ80 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC5553MVZ80 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 66 page  MPC5553 Microcontroller Data Sheet, Rev. 2.0 Overview Freescale Semiconductor 2 contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. The internal SRAM and flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or 100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. |
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