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MPC8541CPXAJF Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

Part # MPC8541CPXAJF
Description  PowerQUICC??III Integrated Communications Processor Hardware Specifications
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8541CPXAJF Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
2
Freescale Semiconductor
Overview
1
Overview
The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the
major functional units within the MPC8541E.
.
Figure 1. MPC8541E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8541E feature set.
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
I2C Controller
Local Bus Controller
64/32b PCI Controller
0/32b PCI Controller
DMA Controller
10/100/1000 MAC
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Serial
DMA
ROM
I-Memory
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
FCC
FCC
SPI
I2C
MIIs/RMIIs
I/Os
CPM
DDR SDRAM Controller
CPM
Controller
Interrupt
256 Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
Core Complex
e500
Coherency
Module
OCeaN
IRQs
SDRAM
DDR
GPIO
32b
Programmable
Interrupt Controller
Bus
DUART
Security
Engine


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