MPXY8021A

Sensors

2

Freescale Semiconductor

Figure 1. MPXY8021A Sensor Block Diagram

OPERATING MODES

The device has several operating modes dependent on

the applied voltages to the S1 and S0 pins as shown in

Table 1. In all the modes listed the channel multiplexers, D/A

Register, LFO, and the output pulse dividers will always be

powered up as long as there is a voltage source connected to

When only the S0 pin is at a logic one the pressure

measuring circuit in the device is powered up and the

pressure output signal is connected to the sample capacitor

through a multiplexer. When the S0 pin returns to the low

state the multiplexer will first turn off to store the signal on the

sample capacitor before powering down the measuring

circuitry.

When only the S1 pin is at a logic one the temperature

measuring circuit in the device is powered up and the

temperature output signal is connected to the sample

capacitor through a multiplexer. When the S1 pin returns to

the low state the multiplexer will first turn off to store the signal

on the sample capacitor before powering down the

measuring circuitry.

NOTE: All of the EEPROM trim bits will be powered up

regardless of whether the pressure or temperature

measuring circuitry is activated.

NOTE: If the voltage on the S1 pin exceeds 2.5 times the

its Trim/Test Mode.

reduce current consumption, it is important that all

input pins be driven LOW to avoid powering up the

device.

If any input pin (S1, S0, DATA, or CLK) is driven HIGH

powered up through an ESD protection diode. Such a case

should be avoided. The effective source voltage of the device

will be less than the applied voltage due to diode voltage

drop. In addition, the entire source current will be drawn from

the input pin.

8-Bit

Current

Source

+

-

f

LF

Digital

Control

Power

Control

Clock

Gen

P-Cell

C to V

Convert

AMP

Internal HF

OSC.

P-Off

Trim

P-Gain

Trim

P-TCO

Trim

P-TCS

Trim

T-Off

Trim

2-Chan

MUX

t

PTC

Res.

2-Chan

MUX

S1

S0

CLK

Data

RST

OUT

COMP

3-Chan

MUX

Lock

Internal LF

OSC.

14-Stage

Divider

Sample CAP

10-Stage

|Divider

8-Bit

D/A

Register