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XR16C850IJ Datasheet(PDF) 4 Page - Exar Corporation |
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XR16C850IJ Datasheet(HTML) 4 Page - Exar Corporation |
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4 / 56 page  XR16C850 xr 2.97V TO 5.5V UART WITH 128-BYTE FIFO REV. 2.3.1 4 CS0 14 9 I Chip Select 0 input (active high). This input selects the XR16C850 device. If CS1 or CS2# is used as the chip select then this pin must be connected to VCC. During PC Mode, this pin becomes A5. Caution: SEE”FACTORY TEST MODE” ON PAGE 7. CS1 15 10 I Chip Select 1 input (active high). This input selects the XR16C850 device. If CS0 or CS2# is used as the chip select then this pin must be connected to VCC. During PC Mode, this pin becomes A6. Caution: SEE”FACTORY TEST MODE” ON PAGE 7. CS2# 16 11 I Chip Select 2 input (active low). This input selects the XR16C850 device. If CS0 or CS1 is used as the chip select then this pin must be connected to GND. During PC Mode, this pin becomes A7. Caution: SEE”FACTORY TEST MODE” ON PAGE 7. INT 33 30 O Interrupt Output. This output becomes active whenever the transmitter, receiver, line and/or modem status register has an active condition and is enabled by IER. See interrupt section for more details. During PC mode, this pin becomes IRQA. RXRDY# 32 29 O Receive Ready (active low). A logic 0 indicates receive data ready status, i.e. the RHR is full or the FIFO has one or more RX characters available for unloading. For details, see Table 2. During PC Mode, this pin becomes IRQB. TXRDY# 27 23 O Transmit Ready (active low). Buffer ready status is indicated by a logic 0, i.e. at least one location is empty and available in the FIFO or THR. For details, see Table 2. During PC Mode, this pin becomes IRQC. AS# 28 24 I Address Strobe input (active low). In the Intel bus mode, the leading-edge transition of AS# latches the chip selects (CS0, CS1, CS2#) and the address lines A0, A1 and A2. This input is used when the address lines are not stable for the duration of a read or write operation. In devices with top mark date code of "F2 YYWW" and newer, the address bus is latched even if this input is not used. These devices fea- ture a ’0 ns’ address hold time. See “AC Electrical Characteristics” . If not required, this input can be permanently tied to GND. During PC Mode, this pin becomes AEN#. D10 D11 D12 - - - 48 1 22 O High order data bus. When BUS8/16 is selected as 16 bit data bus mode (BUS8/16 is grounded), RX data errors (break, parity, framing) can be read via these pins. D10 = Parity, D11 = Framing, and D12 = Break. When BUS8/16 is selected as 8 bit data bus mode (BUS8/16 is at VCC), D10 and D11 are inactive and D12 becomes DDIS#. During PC Mode, D10 and D11 are inactive and D12 becomes LPT2#. BUS8/16 - 25 I 8 or 16 Bit Bus select. For normal 8 bit operation, this pin should be connected to VCC or left open. To select 16 bit bus mode, this pin should be connected to GND. When 16 bit bus mode is enabled, DDIS# becomes D12. 16 bit bus mode is not available for PC Mode. Only RX data error will be provided during this operation. This pin has an internal pull-up resistor. CLKSEL - 13 I Clock Select. The div-by-1 or div-by-4 pre-scaleable clock is selected by this pin. The div-by-1 clock is selected when CLKSEL is connected to VCC or the div-by-4 is selected when CLKSEL is connected to GND. MCR bit-7 can override the state of this pin following reset or initialization (see MCR bit-7). This pin is not available on 40 and 44 pin packages which provide MCR bit-7 selection only. This pin has an internal pull-up resistor. RCLK 10 5 I This input is used as external 16X clock input to the receiver section. If not used, connect the -BAUDOUT pin to this input externally. During PC Mode, this pin becomes S2. NAME 44-PIN PLCC 48-PIN TQFP TYPE DESCRIPTION |
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