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XR16V654IL Datasheet(PDF) 1 Page - Exar Corporation |
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XR16V654IL Datasheet(HTML) 1 Page - Exar Corporation |
1 / 58 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO MAY 2007 REV. 1.0.1 GENERAL DESCRIPTION The XR16V6541 (V654) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 64 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The V654 is available in a 48- pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP and 100-pin QFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48, 68 and 100 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16V654IV (64-pin) offers three state interrupt output while the XR16V654DIV provides continuous interrupt output. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The XR16V654 is compatible with the industry standard ST16C554 and ST16C654/654D. NOTE: 1 Covered by U.S. Patent #5,649,122. FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, TI’s TL16C754B and Philip’s SC16C654B • Intel or Motorola Data Bus Interface select • Four independent UART channels ■ Register Set Compatible to 16C550 ■ Data rates of up to 16 Mbps ■ 64 Byte Transmit FIFO ■ 64 Byte Receive FIFO with error tags ■ 4 Selectable TX and RX FIFO Trigger Levels ■ Automatic Hardware (RTS/CTS) Flow Control ■ Automatic Software (Xon/Xoff) Flow Control ■ Progammable Xon/Xoff characters ■ Wireless Infrared (IrDA 1.0) Encoder/Decoder ■ Full modem interface • 2.25V to 3.6V supply operation • Sleep Mode with automatic wake-up • Crystal oscillator or external clock input APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16V654 BLOCK DIAGRAM XTAL1 XTAL2 Crystal Osc/Buffer Data Bus Interface UART Channel A 64 Byte TX FIFO 64 Byte RX FIFO BRG IR ENDEC TX & RX UART Regs 2.25V to 3.6V VCC GND 654 BLK TXB, RXB, IRTXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# UART Channel B (same as Channel A) A2:A0 D7:D0 CSA# 16/68# CSB# INTA INTB IOW# IOR# Reset INTSEL CHCCLK TXRDY# A-D RXRDY# A-D UART Channel C (same as Channel A) TXA, RXA, IRTXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA# TXC, RXC, IRTXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# UART Channel D (same as Channel A) TXD, RXD, IRTXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# CSC# CSD# INTC INTD CLKSEL * 5 Volt Tolerant Inputs (Except XTAL1 input) |
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