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XR16V2651IM Datasheet(PDF) 9 Page - Exar Corporation |
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XR16V2651IM Datasheet(HTML) 9 Page - Exar Corporation |
9 / 51 page XR16V2651 9 REV. 1.0.2 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.3 Device Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.4 Device Identification and Revision The XR16V2651 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will provide 0x06 for the XR16V2651 and reading the content of DREV will provide the revision of the part; for example, a reading of 0x01 means revision A. 2.5 Channel A and B Selection The UART provides the user with the capability to bi-directionally transfer information between an external CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers, but do not attempt to read from both UARTs simultaneously. Individual channel select functions are shown in Table 1. During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for connection with Motorola, and other popular microprocessor bus types. In this mode the V2651 decodes an additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in the Motorola Bus Mode. See Table 2. Each UART channel in the V2651 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/ LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/ DLM/DLD), and a user accessible Scratchpad Register (SPR). Beyond the general 16C2550 features and capabilities, the V2651 offers enhanced feature registers (EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, and Xon/Xoff software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 23. TABLE 1: CHANNEL A AND B SELECT IN 16 MODE CSA# CSB# FUNCTION 1 1 UART de-selected 0 1 Channel A selected 1 0 Channel B selected 0 0 Channel A and B selected TABLE 2: CHANNEL A AND B SELECT IN 68 MODE CS# A3 FUNCTION 1 N/A UART de-selected 0 0 Channel A selected 0 1 Channel B selected |
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