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XRT75R12D Datasheet(PDF) 5 Page - Exar Corporation |
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XRT75R12D Datasheet(HTML) 5 Page - Exar Corporation |
5 / 134 page XRT75R12D III REV. 1.0.1 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 24: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)....................................................... 64 TABLE 25: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E) ........................................................................... 64 TABLE 26: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F) ......................................................................... 65 THE PER-CHANNEL REGISTERS........................................................................................................................... 66 REGISTER DESCRIPTION - PER CHANNEL REGISTERS ....................................................................................66 TABLE 27: XRT75R12D REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) ............................................................... 66 TABLE 28: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1 .................................................... 67 TABLE 29: XRT75R12D REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N)........................................................................ 69 TABLE 30: XRT75R12 REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N) .......................................................................... 71 TABLE 31: XRT75R12D REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N) ................................................................ 75 TABLE 32: XRT75R12D REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N).................................................................. 77 TABLE 33: XRT75R12D REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N)................................................................. 79 TABLE 34: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N)................................................. 81 TABLE 35: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) ..................................................... 82 TABLE 36: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA................................................................. 83 TABLE 37: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) ....................................................... 83 TABLE 38: ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB.................................................................. 84 TABLE 39: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) ..................................................... 84 TABLE 40: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC ................................................................ 85 8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 86 8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 86 FIGURE 37. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 87 8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 88 8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 88 FIGURE 38. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 89 FIGURE 39. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED 90 FIGURE 40. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 91 FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 92 FIGURE 42. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 93 FIGURE 43. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE ......... 94 FIGURE 44. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN STS-1 SPE.......................................................................................................................................................................... 94 8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 95 FIGURE 45. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .................................... 96 FIGURE 46. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .................................................................................. 98 FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL................................................................................... 99 8.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 99 8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER......................................................................................................... 100 FIGURE 48. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES ......................................... 100 FIGURE 49. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF THE J1 BYTE, DESIGNATED .................................................................................................................................................. 101 FIGURE 50. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ................................................ 101 8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK ................................................................................ 101 8.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................. 102 FIGURE 51. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER.................................................................. 103 FIGURE 52. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DES- IGNATED ............................................................................................................................................................................. 104 FIGURE 53. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DES- IGNATED ............................................................................................................................................................................. 105 8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................. 106 8.4 CLOCK GAPPING JITTER ........................................................................................................................... 106 FIGURE 54. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION ...................................... 106 8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 APPLICATIONS .......................................................................................................................... 107 TABLE 41: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS ...... 107 8.5.1 DS3 DE-MAPPING JITTER....................................................................................................................................... 108 8.5.2 SINGLE POINTER ADJUSTMENT ........................................................................................................................... 108 FIGURE 55. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ............................................................................................. 108 8.5.3 POINTER BURST...................................................................................................................................................... 109 FIGURE 56. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ......................................................................................... 109 8.5.4 PHASE TRANSIENTS............................................................................................................................................... 109 |
Similar Part No. - XRT75R12D_06 |
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Similar Description - XRT75R12D_06 |
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