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ST78C36/36A

REV. 5.0.2

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

7

DCR Bit-1:

The complement of this bit drives -AUTOFD, and the complement of the pad state is returned for read.

DCR Bit-2:

This bit drives INIT, and the pad state is returned for read.

DCR Bit-3:

The complement of this bit drives -SLCTIN, and the complement of the pad state is returned for read.

DCR Bit-4:

Ack Interrupt Enable set to a high will generate an interrupt when -ACK is low. When either returns to a high

state, this interrupt source will go in-active. This interrupt is not pulsed.

DCR Bit-5:

Peripheral port direction, OUT = 0 and IN = 1.

This bit is forced to logic zero by ECR modes 000 or 010. It can be written only in ECR mode 001, and will

maintain that state if the ECR mode is changed to 011, 100, or 110. This bit must be set low for EPP mode,

which allows the host to control direction with -IOR and -IOW. The final port direction also drives PDIR.

DCR Bits 6-7:

Reserved, logic zero.

3.5

EPP ADDRESS PORT ( EPP-APort )

When EPP mode is enabled, a host read or write with this port will result in a data transfer directly to/from the

peripheral with -SLCTIN active. Direction is set by host read/write and will drive -STROBE low during a write if

DCR bit 5 (DIR) is not set high.

3.6

EPP DATA PORT (EPP-DPort )

When EPP mode is enabled, a host read or write with this port will result in a data transfer directly to/from the

peripheral with -AUTOFD active. Direction is set by host read/write and will drive -STROBE low during a write

if DCR bit 5 (DIR) is not set high.

3.7

PARALLEL PORT DATA ( C-FIFO )

This port is available for programmed I/O and DMA access. Data written to this port is stored in the FIFO if

FIFO-F = 0 and will be lost if FIFO-F = 1.

Data written to this port will be automatically transferred to the peripheral with -STROBE handshaking with

BUSY. This port is only defined for write, host reads will interfere with FIFO read sequencing.

3.8

ECP DATA FIFO ( ECP-DFIFO )

This port is available for programmed I/O and DMA access. Data written to this port is stored in the FIFO if

FIFO-F = 0 and will be lost if FIFO-F = 1. A 9th FIFO bit (tag) is set high on write.

Data read from this port will undergo de-compression if the FIFO tag bit and data bit-7 are both low. The byte

containing the RLE count is loaded into the RLE counter and the succeeding byte in the FIFO will be returned

to the host RLE count + 1 times before the FIFO read address is incremented. If a FIFO under-run is incurred

during host read, the last data byte is returned and FIFO-E remains coherent.

3.9

TEST FIFO ( T-FIFO )

This port is available for programmed I/O and DMA access. Data written to this port is stored in the FIFO if

FIFO-F = 0 and will be lost if FIFO-F = 1. During a read cycle from this port a FIFO under-run will return last

data read and FIFO-E remains coherent.

3.10

CONFIGURATION REGISTER A ( Cnfg-A )

This read-only register is available in ECR mode 111 only.

Cnfg-A Bits 1-0:

Forced to logic zero, this field is don’t care for PWord = 1 byte.