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XRT79L71IB Datasheet(PDF) 11 Page - Exar Corporation

Part # XRT79L71IB
Description  1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT79L71IB Datasheet(HTML) 11 Page - Exar Corporation

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XRT79L71
8
REV. 1.0.0
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
C14
RDY/DTACK/
RDY
O
READY or DTACK Output:
The exact function of this input pin depends upon which mode the Microprocessor
Interface has been configured to operate in.
Intel-Asynchronous Mode - RDY - Ready Output:
If the Microprocessor Interface has been configured to operate in the Intel-Asynchro-
nous Mode, then this output pin functions as the active-"Low" READY output.
During a READ or WRITE cycle, the Microprocessor Interface block toggles this out-
put pin to the logic "Low" level ONLY when it (the Microprocessor Interface) is ready
to complete or terminate the current READ or WRITE cycle. Once the Microproces-
sor has determined that this input pin has toggled to the logic "Low" level, then it is
now safe for it to move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this
output pin at a logic "High" level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being toggled to the logic "Low"
level.
Motorola-Asynchronous Mode - DTACK - Data Transfer Acknowledge Output
If the Microprocessor Interface has been configured to operate in the Motorola-Asyn-
chronous Mode, then this output pin will function as the active-"Low" DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface block will toggle this
output pin to the logic "Low" level, ONLY when it (the Microprocessor Interface) is
ready to complete or terminate the current READ or WRITE cycle. Once the Micro-
processor has determined that this input pin has toggled to the logic "Low" level, then
it is now safe for it to move on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this
output pin at a logic "High" level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being toggled to the logic "Low"
level.
Power PC 403 Mode - RDY - Ready Output:
If the Microprocessor Interface has been configured to operate in the Power PC 403
Mode, then this output pin will function as the active-"High" READY output.
During a READ or WRITE cycle, the Microprocessor Interface block toggles this out-
put pin to the logic "High" level ONLY when it (the Microprocessor Interface) is ready
to complete or terminate the current READ or WRITE cycle. Once the Microproces-
sor has sampled this signal being at the logic "High" level (upon the rising edge of
PCLK), then it is now safe for it to move on and execute the next READ or WRITE
cycle.
If during a READ or WRITE cycle the Microprocessor Interface block is holding this
output pin at a logic "Low" level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it samples this output pin being at the logic "Low" level.
NOTE: The Microprocessor Interface updates the state of this output pin upon the
rising edge of mPCLK.
M14
RESET
I
Hardware Reset Input:
When this active-"Low" signal is asserted, the XRT79L71 will be asynchronously
reset. When this occurs, all outputs will be tri-stated and all on-chip registers will be
reset to their default values.
PIN DESCRIPTIONS
PIN #NAME
TYPE
DESCRIPTION


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