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XRT82L24AIV Datasheet(PDF) 1 Page - Exar Corporation |
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XRT82L24AIV Datasheet(HTML) 1 Page - Exar Corporation |
1 / 39 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç áç áç áç XRT82L24A QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR AUGUST 2004 REV. 1.1.2 GENERAL DESCRIPTION The XRT82L24A is a fully integrated Quad (four chan- nels) short-haul line interface unit for E1(2.048Mbps) 75 Ω or 120Ω applications. Each channel consists of a receiver with equalizer for reliable data and clock re- covery, and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low output impedance line driver. The de- vice also includes a crystal-less jitter attenuator which, depending on system requirements, can be selected in the receive or transmit path through the Host or Hardware Mode control. XRT82L24A is a low power CMOS device operating on a single 3.3V supply with 5V tolerant digital inputs. FEATURES • Fully integrated quad, short-haul PCM transceivers for E1 applications. • On Chip Receive Equalizer and Transmit Pulse Shaper for CEPT 75 Ω and 120Ω line terminations • On chip clock recovery circuit • Transformer or capacitor coupled receiver inputs • Crystal-less jitter attenuator can be selected in the transmit or receive path • High receiver interference immunity • Per-channel transmit power shutdown • Tri-state transmit output capability • On chip per-channel driver failure monitoring circuit • On chip HDB3/B8ZS/AMI encoder/decoder func- tions • Supports Gapped Clock for Multiplexer Mapper Applications • Transmit return loss meets or exceeds ETSI 300 166 standard • Meets or exceeds specifications in ITU G.703, G.775, G.736 and G.823; ETSI 300-166 • Meets or exceeds G.783 and G.823 Jitter Specifi- cations • 3.3V or 5.0V Logic level inputs • Single +3.3V Supply Operation • New Patent# 6,313,671B1 Low Power IC I/O Buffer APPLICATIONS • Digital cross connects (DSX-1) • Channel Banks • High speed data transmission line cards • E1 Multiplexer • Public switching systems and PBX interfaces FIGURE 1. BLOCK DIAGRAM OF THE XRT82L24A E1 LIU (HOST MODE) HDB3 Encoder MUX Tx/Rx Jitter Attenuator Tx Timing Control Tx Pulse Shaper MUX Line Driver Tx/Rx Jitter Attenuator Timing & Data Recovery Peak Detector & Slicer Rx Equalizer LOS Detect HDB3 Decoder Clock Generator MClk TVDD_n TTIP_n TRing_n TGND_n Enable/ Disable RTIP_n RRing_n Remote LoopBack Local Analog LoopBack Digital LoopBack Driver Monitor Channel 0 Channel 1 Channel 2 Channel 3 HW/HOST µµµµP Controller & Hardware Interface ADD [0:3] D[0:7] WR_R/W/TxOFF_0 ALE_AS/TxOFF_2 CS/TxOFF_3 RD_DS/TxOFF_1 Test TxClk_n/RZData_n TxPOS_n/TDATA_n TxNEG_n RxClk_n RxPOS_n/RDATA_n RxNEG_n/LCV_n RxLOS_n INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR_DR Reset ICT |
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