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XRT83L30 Datasheet(PDF) 8 Page - Exar Corporation |
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XRT83L30 Datasheet(HTML) 8 Page - Exar Corporation |
8 / 78 page XRT83L30 5 SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 PIN DESCRIPTIONS BY FUNCTION SERIAL INTERFACE SIGNAL NAME PIN # TYPE DESCRIPTION HW/HOST 20 I Mode Control Input This pin is used for selecting Hardware or Host mode to control the device. Leave this pin unconnected or tie “High” to select Hardware mode. For Host mode, this pin must be tied “Low”. NOTE: Internally pulled “High” with a 50k Ω resistor. SDI EQC4 21 I Serial Data Input In Host mode, this pin is the data input for the Serial Interface. Equalizer Control Input 4 Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13. SDO EQC3 22 O I Serial Data Output In Host mode, this pin is the output “Read” data for the serial interface. Equalizer Control Input 3 Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13. SCLK EQC2 23 I Serial Interface Clock Input In Host mode, this clock signal is used to control data “Read” or “Write” oper- ation for the Serial Interface. Maximum clock frequency is 20MHz. Equalizer Control Input 2 Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13. CS EQC1 24 I Chip Select Input In Host mode, tie this pin “Low” to enable communication with the device via the Serial Interface. Equalizer Control Input 1 Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13. INT EQC0 25 O I Interrupt Output (active "Low") In Host mode, this pin goes “Low” to indicate an alarm condition has occurred within the device. Interrupt generation can be globally disabled by setting the GIE bit to “0” in the command control register. Equalizer Control Input 0 Hardware mode, SEE”CONTROL FUNCTION” ON PAGE 13. NOTE: This pin is an open drain output and requires an external 10k Ω pull- up resistor. |
Similar Part No. - XRT83L30_06 |
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Similar Description - XRT83L30_06 |
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