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XRT83L34 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT83L34 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 99 page xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.1 I TABLE OF CONTENTS GENERAL DESCRIPTION.................................................................................................... 1 APPLICATIONS................................................................................................................................................ 1 Figure 1. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ........................................... 1 Figure 2. Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode)................................... 2 FEATURES ..................................................................................................................................................... 2 ORDERING INFORMATION ....................................................................................................................... 3 Figure 3. Pin Out of the XRT83L34.................................................................................................... 4 TABLE OF CONTENTS ..................................................................................................... I PIN DESCRIPTION BY FUNCTION...................................................................................... 5 RECEIVE SECTIONS........................................................................................................................................ 5 TRANSMITTER SECTIONS ................................................................................................................................9 MICROPROCESSOR INTERFACE ..................................................................................................................... 13 JITTER ATTENUATOR .................................................................................................................................... 19 CLOCK SYNTHESIZER ................................................................................................................................... 20 ALARM FUNCTION//REDUNDANCY SUPPORT .................................................................................................. 21 POWER AND GROUND ................................................................................................................................... 25 FUNCTIONAL DESCRIPTION ............................................................................................ 26 MASTER CLOCK GENERATOR ....................................................................................................................... 26 Figure 4. Two Input Clock Source................................................................................................... 26 Figure 5. One Input Clock Source ................................................................................................... 26 TABLE 1: MASTER CLOCK GENERATOR ................................................................................................ 27 RECEIVER........................................................................................................................... 27 RECEIVER INPUT .......................................................................................................................................... 27 RECEIVE MONITOR MODE............................................................................................................................. 28 RECEIVER LOSS OF SIGNAL (RLOS)............................................................................................................. 28 Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 28 Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition.......................... 29 Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ................ 29 Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 30 RECEIVE HDB3/B8ZS DECODER ................................................................................................................. 30 RECOVERED CLOCK (RCLK) SAMPLING EDGE .............................................................................................. 30 Figure 10. Receive Clock and Output Data Timing ....................................................................... 30 JITTER ATTENUATOR .................................................................................................................................... 30 GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) .................................................................. 31 TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ......................................... 31 ARBITRARY PULSE GENERATOR FOR T1 AND E1 ........................................................................................... 32 Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 32 TRANSMITTER ................................................................................................................... 32 DIGITAL DATA FORMAT................................................................................................................................. 32 TRANSMIT CLOCK (TCLK) SAMPLING EDGE .................................................................................................. 32 Figure 12. Transmit Clock and Input Data Timing ......................................................................... 33 TRANSMIT HDB3/B8ZS ENCODER................................................................................................................ 33 TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... 33 TABLE 4: EXAMPLES OF B8ZS ENCODING ............................................................................................ 33 DRIVER FAILURE MONITOR (DMO) ............................................................................................................... 33 TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT........................................................................ 34 TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ............................ 34 TRANSMIT AND RECEIVE TERMINATIONS .................................................................... 36 RECEIVER (CHANNELS 0 - 3) ..................................................................................................................... 36 Internal Receive Termination Mode ............................................................................................................ 36 TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 36 Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode......... 36 |
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