Electronic Components Datasheet Search |
|
XRT83L34 Datasheet(PDF) 1 Page - Exar Corporation |
|
XRT83L34 Datasheet(HTML) 1 Page - Exar Corporation |
1 / 99 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR FEBRUARY 2005 REV. 1.0.1 GENERAL DESCRIPTION The XRT83L34 is a fully integrated Quad (four channel) long-haul and short-haul line interface unit for T1 (1.544Mbps) 100 Ω, E1 (2.048Mbps) 75Ω or 120 Ω, or J1 110Ω applications. In long-haul applications the XRT83L34 accepts signals that have been attenuated from 0 to 36dB at 772kHz in T1 mode (equivalent of 0 to 6000 feet of cable loss) or 0 to 43dB at 1024kHz in E1 mode. In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements as well as for Channel Service Units (CSU) Line Build Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB as required by FCC rules. It also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The XRT83L34 provides both a parallel Host microprocessor interface as well as a Hardware mode for programming and control. Both the B8ZS and HDB3 encoding and decoding functions are selectable as well as AMI. An on-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83L34 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75 Ω, 100 Ω, 110Ω and 120Ω for both transmitter and receiver. In the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HOST MODE) One of four channels, CHANNEL_n - (n= 0:3) HW /HO ST WR_R/W RD_DS ALE_AS CS RDY_DT ACK INT ICT TPOS_n/TDATA_n TNEG_n/CO DES_n TCLK_n RCLK_n RNEG_n/LCV_n RPOS_n/RDATA_n RLOS_n RTIP_n RRING_n M AST ER CLOCK SYNT HESIZER QRSS PAT T ERN G ENERAT O R DMO_n TTIP_n TRING_n TXON_n HDB3/ B8ZS ENCODER TX/RX JITT ER AT T ENUAT OR TIMING CO NT ROL T X FILT ER & PULSE SHAPER LINE DRIVER DRIVE MO NIT OR LOCAL ANALOG LOOPBACK REMO T E LOOPBACK DIGIT AL LO OPBACK HDB3/ B8ZS DECODER TX/RX JITT ER AT T ENUAT OR TIMING & DAT A RECOVERY PEAK DET ECT O R & SLICER QRSS DET ECT OR NET W ORK LO OP DET ECT OR RX EQ UALIZER EQUALIZER CO NT ROL AIS DET ECT O R LOS DET ECT O R LBO[3:0] LO OPBACK ENABLE NLCD ENABLE QRSS ENABLE µ PTS1 µ PTS2 D[7:0] µ PCLK A[7:0] RESET M ICROPROCESSOR CONT RO LLER TEST DFM TAO S ENABLE MCLKE1 MCLKT1 MCLKO UT |
Similar Part No. - XRT83L34 |
|
Similar Description - XRT83L34 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |