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XRT83SH314 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT83SH314 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 101 page XRT83SH314 II REV. 1.0.4 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 18. TAOS (TRANSMIT ALL ONES) ............................................................................................................................................ 27 3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27 3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 28 FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 28 3.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28 TABLE 10: RANDOM BIT SEQUENCE POLYNOMIALS................................................................................................................................28 3.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28 3.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 29 TABLE 11: SHORT HAUL LINE BUILD OUT.............................................................................................................................................. 29 3.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29 FIGURE 20. ARBITRARY PULSE SEGMENT ASSIGNMENT ......................................................................................................................... 29 3.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE ................................................................................. 30 TABLE 12: TYPICAL ROM VALUES ........................................................................................................................................................ 30 3.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30 3.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30 FIGURE 21. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 31 4.0 T1/E1 APPLICATIONS ........................................................................................................................ 32 4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32 4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32 FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 32 4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 32 FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 32 4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 33 FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 33 4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33 FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ............................................................................................................... 33 4.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 34 FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ........................................................................................... 34 TABLE 13: CHIP SELECT ASSIGNMENTS ................................................................................................................................................ 34 4.3 LINE CARD REDUNDANCY .......................................................................................................................... 35 4.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 35 4.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 35 FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY................................................ 35 4.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 36 FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY.................................................. 36 4.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36 4.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 37 FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ............................................................ 37 4.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 38 FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY .............................................................. 38 4.4 POWER FAILURE PROTECTION .................................................................................................................. 39 4.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 39 4.6 NON-INTRUSIVE MONITORING .................................................................................................................... 39 FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION ..................................................................... 39 4.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 40 FIGURE 32. ATP TESTING BLOCK DIAGRAM ........................................................................................................................................... 40 FIGURE 33. TIMING DIAGRAM FOR ATP TESTING ................................................................................................................................. 40 4.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 40 4.7.2 RECEIVER RTIP AND RRING .................................................................................................................................... 41 4.8 XRT83SH314 JITTER CHARACTERISTICS .................................................................................................. 42 4.8.1 JITTER TOLERANCE ................................................................................................................................................. 42 FIGURE 34. TEST CIRCUIT FOR DS-1 JITTER TOLERANCE...................................................................................................................... 42 FIGURE 35. GR-499 JITTER TOLERANCE MASK .................................................................................................................................... 42 FIGURE 36. DS-1 JITTER TOLERANCE................................................................................................................................................... 43 FIGURE 37. DS-1 JITTER TRANSFER CURVE VARIABLE AMPLITUDE - T1 JA DISABLE......................................................................... 44 FIGURE 38. JITTER TRANSFER FUNCTION VARIABLE AMPLITUDE - T1 TX 3HZ 32BITS ........................................................................... 45 FIGURE 39. JITTER TRANSFER FUNCTION - T1 TX 3HZ 64BITS .............................................................................................................. 46 FIGURE 40. JITTER TRANSFER FUNCTION - T1 RX 3HZ 32BITS ........................................................................................................... 47 FIGURE 41. JITTER TRANSFER FUNCTION - T1 RX 3HZ 64BITS ............................................................................................................ 48 FIGURE 42. TEST CIRCUIT FOR E1 JITTER TOLERANCE ......................................................................................................................... 49 FIGURE 43. ITU-G.823 JITTER TOLERANCE MASK ................................................................................................................................49 FIGURE 44. REVISION C: E1 JITTER TOLERANCE - 6DB CABLE + 6DB FLAT LOSS ................................................................................... 50 FIGURE 45. JITTER TRANSFER FUNCTION - JA DISABLED ...................................................................................................................... 51 FIGURE 46. JITTER TRANSFER FUNCTION - E1 TX 10HZ 32BITS.......................................................................................................... 52 FIGURE 47. JITTER TRANSFER FUNCTION - E1 TX 10HZ 64BITS.......................................................................................................... 53 |
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