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XRT83SL38 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT83SL38 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 88 page XRT83SL38 I REV. 1.0.2 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR TABLE OF CONTENTS GENERAL DESCRIPTION .................................................................................................. 1 APPLICATIONS .............................................................................................................................................. 1 Figure 1. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Host Mode) ........................................ 1 Figure 2. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Hardware Mode) ............................... 2 FEATURES ................................................................................................................................................... 2 ORDERING INFORMATION ............................................................................................................... 3 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTION BY FUNCTION .................................................................................... 6 RECEIVE SECTIONS ...................................................................................................................................... 6 TRANSMITTER SECTIONS .............................................................................................................................. 8 MICROPROCESSOR INTERFACE ................................................................................................................... 12 JITTER ATTENUATOR .................................................................................................................................. 15 CLOCK SYNTHESIZER ................................................................................................................................. 15 ALARM FUNCTIONS/REDUNDANCY SUPPORT ............................................................................................... 17 POWER AND GROUND ................................................................................................................................ 20 PINS ONLY AVAILABLE IN BGA PACKAGE .......................................................................................... 22 FUNCTIONAL DESCRIPTION .......................................................................................... 23 MASTER CLOCK GENERATOR ..................................................................................................................... 23 Figure 3. Two Input Clock Source .................................................................................................. 23 Figure 4. One Input Clock Source .................................................................................................. 23 TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 24 RECEIVER ......................................................................................................................... 24 RECEIVER INPUT ........................................................................................................................................ 24 RECEIVE MONITOR MODE ........................................................................................................................... 25 RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 25 Figure 5. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition .............. 25 Figure 6. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 26 RECEIVE HDB3/B8ZS DECODER ............................................................................................................... 26 RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 26 Figure 7. Receive Clock and Output Data Timing ........................................................................ 26 JITTER ATTENUATOR .................................................................................................................................. 27 GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................ 27 TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 27 ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... 28 Figure 8. Arbitrary Pulse Segment Assignment ........................................................................... 28 TRANSMITTER ................................................................................................................. 28 DIGITAL DATA FORMAT ............................................................................................................................... 28 TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 28 Figure 9. Transmit Clock and Input Data Timing .......................................................................... 29 TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 29 TABLE 3: EXAMPLES OF HDB3 ENCODING .......................................................................................... 29 TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 29 DRIVER FAILURE MONITOR (DMO) ............................................................................................................. 29 TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 30 TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 30 TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 31 RECEIVER (CHANNELS 0 - 7) ................................................................................................................... 31 Internal Receive Termination Mode ..................................................................................................................... 31 TABLE 6: RECEIVE TERMINATION CONTROL ......................................................................................... 31 Figure 10. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 31 TABLE 7: RECEIVE TERMINATIONS ....................................................................................................... 33 Figure 11. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 33 |
Similar Part No. - XRT83SL38_07 |
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Similar Description - XRT83SL38_07 |
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