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XRT83SH314IB Datasheet(PDF) 4 Page - Exar Corporation |
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XRT83SH314IB Datasheet(HTML) 4 Page - Exar Corporation |
4 / 101 page XRT83SH314 I 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.4 TABLE OF CONTENTS GENERAL DESCRIPTION.............................................................................................................. 1 APPLICATIONS .......................................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH314 ................................................................................................................................. 1 FEATURES ..................................................................................................................................................................... 1 PRODUCT ORDERING INFORMATION................................................................................................................................2 PIN OUT OF THE XRT83SH314..................................................................................................................................... 3 TABLE OF CONTENTS ............................................................................................................I PIN DESCRIPTIONS (BY FUNCTION) ........................................................................................... 4 MICROPROCESSOR ........................................................................................................................................................ 4 RECEIVER SECTION ....................................................................................................................................................... 5 TRANSMITTER SECTION.................................................................................................................................................. 8 CONTROL FUNCTION.................................................................................................................................................... 10 CLOCK SECTION .......................................................................................................................................................... 10 JTAG SECTION ........................................................................................................................................................... 10 POWER AND GROUND .................................................................................................................................................. 11 NO CONNECTS ............................................................................................................................................................ 13 1.0 CLOCK SYNTHESIZER .......................................................................................................................14 TABLE 1: INPUT CLOCK SOURCE SELECT .............................................................................................................................................. 14 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER................................................................................................... 15 1.1 ALL T1/E1 MODE ........................................................................................................................................... 15 2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................15 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 15 2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 16 2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 16 TABLE 2: SELECTING THE INTERNAL IMPEDANCE.................................................................................................................................... 16 FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 16 2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 17 TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 17 FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR.............................................................................. 17 2.2 CLOCK AND DATA RECOVERY ................................................................................................................... 18 FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 18 FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................... 18 TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG.................................................................................................................19 2.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 19 FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY .............................................................................................. 19 2.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 20 FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN........................................................................................... 20 2.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 20 FIGURE 10. INTERRUPT GENERATION PROCESS BLOCK ......................................................................................................................... 21 FIGURE 11. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 22 TABLE 5: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 22 2.3 JITTER ATTENUATOR ................................................................................................................................... 23 2.4 HDB3/B8ZS DECODER .................................................................................................................................. 23 2.5 RPOS/RNEG/RCLK ........................................................................................................................................ 24 FIGURE 12. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 24 FIGURE 13. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 24 2.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 24 FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 24 3.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................25 FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 25 3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 25 FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ...................................................................................................... 25 FIGURE 17. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ........................................................................................................ 26 TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 26 3.2 HDB3/B8ZS ENCODER .................................................................................................................................. 26 TABLE 7: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 26 TABLE 8: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 27 3.3 JITTER ATTENUATOR ................................................................................................................................... 27 TABLE 9: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS........................................................................................... 27 3.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 27 |
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