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XRT83VSH28IB Datasheet(PDF) 6 Page - Exar Corporation

Part # XRT83VSH28IB
Description  8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83VSH28IB Datasheet(HTML) 6 Page - Exar Corporation

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XRT83VSH28
PRELIMINARY
II
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.0
3.5.3 ARBITRARY PULSE GENERATOR FOR E1 ............................................................................................................. 30
FIGURE 18. ARBITRARY PULSE SEGMENT ASSIGNMENT .................................................................................................................. 30
3.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30
3.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
FIGURE 19. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 31
4.0 E1 APPLICATIONS ..............................................................................................................................32
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
FIGURE 20. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 32
4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 32
FIGURE 21. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .................................................................................................... 32
4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 33
FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 33
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ........................................................................................................ 33
4.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
4.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34
4.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ......................................... 34
4.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ........................................... 35
4.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
4.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ...................................................... 36
4.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY ........................................................ 37
4.3 POWER FAILURE PROTECTION .................................................................................................................. 38
4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
4.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION............................................................... 38
5.0 MICROPROCESSOR INTERFACE ......................................................................................................39
5.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ................................................................. 39
5.1.1 SERIAL TIMING INFORMATION ................................................................................................................................ 39
FIGURE 30. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ................................................................................ 39
5.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
5.1.3 ADDR[7:0] (SCLK1 - SCLK8) ..................................................................................................................................... 40
5.1.4 R/W (SCLK9) ............................................................................................................................................................... 40
5.1.5 DUMMY BITS (SCLK10 - SCLK16) ............................................................................................................................ 40
5.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
5.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
FIGURE 31. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 41
TABLE 9: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 41
5.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
TABLE 10: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 42
FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK .................................................................. 42
5.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
TABLE 11: XRT83VSH28 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES
43
TABLE 12: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS .................................................................................................... 43
TABLE 13: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ........................................................................................... 44
5.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
FIGURE 33. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................................ 46
TABLE 14: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ........................................................................................ 46
5.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
FIGURE 34. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS............................ 48
TABLE 15: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS........................................................................ 48
TABLE 16: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]).................................................................................................... 49
TABLE 17: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION ................................................................................................... 49
TABLE 18: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION ................................................................................................. 51
TABLE 19: CABLE LENGTH SETTING................................................................................................................................................ 52
TABLE 20: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION ................................................................................................. 52
TABLE 21: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION ................................................................................................. 53
TABLE 22: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION ................................................................................................. 54
TABLE 23: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION ................................................................................................. 55


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