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XRT83VSH314IB Datasheet(PDF) 1 Page - Exar Corporation |
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XRT83VSH314IB Datasheet(HTML) 1 Page - Exar Corporation |
1 / 80 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT83VSH314 is a fully integrated 14-channel short-haul line interface unit (LIU) that operates from a 1.8V Inner Core and 3.3V I/O power supplies. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS/PRBS generation/detection, TAOS, DMO, and diagnostic loopback modes. APPLICATIONS • T1 Digital Cross Connects (DSX-1) • ISDN Primary Rate Interface • CSU/DSU E1/T1/J1 Interface • T1/E1/J1 LAN/WAN Routers • Public Switching Systems and PBX Interfaces • T1/E1/J1 Multiplexer and Channel Banks • Integrated Multi-Service Access Platforms (IMAPs) • Integrated Access Devices (IADs) • Inverse Multiplexing for ATM (IMA) • Wireless Base Stations FIGURE 1. BLOCK DIAGRAM OF THE XRT83VSH314 HDB3/B8ZS Encoder Tx/Rx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen HDB3/B8ZS Decoder Tx/Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer QRSS Generation & Detection AIS & LOS Detector Driver Monitor 1 of 14 Channels Test Microprocessor Interface Programmable Master Clock Synthesizer Line Driver Remote Loopback Digital Loopback Analog Loopback TCLK_n TPOS_n TNEG_n RCLK_n RPOS_n RNEG_n 8kHzOUT MCLKE1out MCLKT1out MCLKE1Nout MCLKT1Nout RTIP_n RRING_n TRING_n TTIP_n TxON RxON ICT RxTSEL TEST DMO RLOS ATP_TIP ATP_RING RCLKOUT |
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