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XRT83VSH314IB Datasheet(PDF) 7 Page - Exar Corporation |
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XRT83VSH314IB Datasheet(HTML) 7 Page - Exar Corporation |
7 / 80 page XRT83VSH314 4 REV. 1.0.1 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 1.0 PIN DESCRIPTIONS MICROPROCESSOR NAME PIN TYPE DESCRIPTION CS A22 I Chip Select Input Active low signal. This signal enables the microprocessor interface by pulling chip select "Low". The microprocessor interface is disabled when the chip select signal returns "High". NOTE: Internally pulled "High" with a 50k Ω resistor. ALE_TS C19 I Address Latch Enable Input (Transfer Start) See the Microprocessor section of this datasheet for a description. NOTE: Internally pulled "Low" with a 50k Ω resistor. WR_R/W A20 I Write Strobe Input (Read/Write) See the Microprocessor section of this datasheet for a description. NOTE: Internally pulled "Low" with a 50k Ω resistor. RD_WE D18 I Read Strobe Input (Write Enable) See the Microprocessor section of this datasheet for a description. NOTE: Internally pulled "Low" with a 50k Ω resistor. RDY_TA AA3 O Ready Output (Transfer Acknowledge) See the Microprocessor section of this datasheet for a description. INT B3 O Interrupt Output Active low signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". GIE (Global Interrupt Enable) must be set "High" in the appropriate global register to enable interrupt generation. NOTE: This pin is an open-drain output that requires an external 10K Ω pull-up resistor. µPCLK AB2 I Micro Processor Clock Input In a synchronous microprocessor interface, µPCLK is used as the internal tim- ing reference for programming the LIU. NOTE: Internally pulled "Low" with a 50k Ω resistor. |
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