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XRT83VSH314IB Datasheet(PDF) 9 Page - Exar Corporation

Part # XRT83VSH314IB
Description  14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83VSH314IB Datasheet(HTML) 9 Page - Exar Corporation

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XRT83VSH314
6
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RxON
AB19
I
Receive On/Off Input
Upon power up, the receivers are powered off. Turning the receivers On or Off
can be selected through the microprocessor interface by programming the
appropriate channel register if the hardware pin is pulled "High". If the hard-
ware pin is pulled "Low", all channels are automatically turned off.
NOTE: Internally pulled "Low" with a 50K
Ω resistor.
RxTSEL
Y15
I
Receive Termination Control
Upon power up, the receivers are in "High" impedance. Switching to internal
termination can be selected through the microprocessor interface by program-
ming the appropriate channel register. However, to switch control to the hard-
ware pin, RxTCNTL must be programmed to "1" in the appropriate global
register. Once control has been granted to the hardware pin, it must be pulled
"High" to switch to internal termination.
NOTE: Internally pulled "Low" with a 50k
Ω resistor.
RLOS
AB1
O
Receive Loss of Signal (Global Pin for All 14-Channels)
When a receive loss of signal occurs for any one of the 14-channels according
to ITU-T G.775, the RLOS pin will go "High" for a minimum of one RCLK cycle.
RLOS will remain "High" until the loss of signal condition clears.
See the
Receive Loss of Signal section of this datasheet for more details.
NOTE: This pin is for redundancy applications to initiate an automatic switch to
the backup card. For individual channel RLOS, see the register map.
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
AB14
Y22
R22
P22
G22
F22
B14
B9
F2
G2
P2
R2
AA2
AA9
O
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent or RxON is pulled "Low", RCLK maintains its timing by using
an internal master clock as its reference. Software control (RCLKE) allows
RPOS/RNEG data to be updated on either edge of RCLK.
NOTE: RCLKE is a global setting that applies to all 14 channels.
RxTSEL (pin)
Rx Termination
External
Internal
0
1
Note: RxTCNTL (bit) must be set to "1"


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