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XRT84L38IB Datasheet(PDF) 1 Page - Exar Corporation

Part # XRT84L38IB
Description  OCTAL T1/E1/J1 FRAMER
Download  453 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT84L38IB Datasheet(HTML) 1 Page - Exar Corporation

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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT84L38
OCTAL T1/E1/J1 FRAMER
SEPTEMBER 2006
REV. 1.0.1
GENERAL DESCRIPTION
The XRT84L38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framing controller. The
XRT84L38 contains an integrated DS1/E1/J1 framer
which
provides
DS1/E1/J1
framing
and
error
accumulation
in
accordance
with
ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers, and
can be independently enabled
or
disabled as
required and can be configured to frame to the
common DS1/E1/J1 signal formats
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function including 3 HDLC
controllers to support V5.2. Each Transmit HDLC
controller encapsulates contents of the Transmit
HDLC buffers into LAPD Message frames. Each
Receive HDLC controller extracts payload content of
Receive LAPD Message frames from the incoming
T1/E1/J1 data stream and writes it into the Receive
HDLC buffer. Each framer also contains a Transmit
and Overhead Data Input port, which permits Data
Link Terminal Equipment direct access
to
the
outbound T1/E1/J1 frames Likewise, a Receive
Overhead output data port permits Data Link Terminal
Equipment direct access to the Data Link bits of the
inbound T1/E1/J1 frames.
The XRT84L38 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995,
ANSI
T1/E1.231-1993,
ANSI
T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions
include
Loop-backs,
Boundary
scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT84L38 8-CHANNEL DS1 (T1/E1/J1) FRAMER
Performance
Monitor
PRBS
Generator &
Analyser
HDLC (LAPD)
Controller &
96-byte Buffer
LIU &
Loopback
Control
DMA
Interface
Signaling &
Alarms
JTAG
WR
ALE_AS
RD
RDY_DTACK
Channel
Select
A[6:0]
D[7:0]
Interrupt
Memory
Microprocessor
Interface
Intel/Motorola µP
Configuration, Control &
Status Monitor
4
3
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
2-Frame
Slip Buffer
Elastic Store
Tx Serial
Data In
Tx Encoder
LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx Encoder
LIU
Interface
Rx Framer
Rx Serial
Data Out
RxPOS
8
RxNEG
8
RxLineCLK 8
TxPOS
8
TxNEG
8
TxLineCLK 8
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
XRT84L38
1 of 8-channels
Tx Framer
LLB
LB
8
8
TPOS
TNEG
TCLK1
RPOS
RNEG
RCLK1
µP
Interface
Tx1
Rx1
Rx8
Tx8
8-CH T1/E1/LIU
Host Mode
XRT83L38
Twisted
Pair
Twisted
Pair
System (Terminal) Side
Line Side
8 DS1/E1
Channels
1.544/2.048 MHz


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