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XRT86L30 Datasheet(PDF) 4 Page - Exar Corporation |
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XRT86L30 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 279 page XRT86L30 I SINGLE T1/E1/J1 FRAMER/LIU COMBO REV. 1.0.0 LIST OF PARAGRAPHS 1.0 PIN LIST ...................................................................................................................................................4 2.0 PIN DESCRIPTIONS ................................................................................................................................5 3.0 MICROPROCESSOR INTERFACE BLOCK ..........................................................................................18 3.0.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ....................................................................................... 18 3.1 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................................. 21 3.2 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) .......................................................... 23 3.2.1 DMA READ/WRITE OPERATIONS .............................................................................................................................. 25 3.3 MEMORY MAPPED I/O ADDRESSING ............................................................................................................ 27 3.4 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................ 28 3.4.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 34 3.5 PROGRAMMING THE LINE INTERFACE UNIT (LIU SECTION) ................................................................... 115 3.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ............................................................................... 133 3.6.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 136 4.0 GENERAL DESCRIPTION AND INTERFACE .....................................................................................139 4.1 PHYSICAL INTERFACE .................................................................................................................................. 139 4.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ................................................ 140 4.2.1 LINE CARD REDUNDANCY ....................................................................................................................................... 140 4.2.2 TYPICAL REDUNDANCY SCHEMES ........................................................................................................................ 140 4.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 140 4.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 140 4.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ..................................................................................... 141 4.3 POWER FAILURE PROTECTION ................................................................................................................... 142 4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ................................................................................ 142 4.5 NON-INTRUSIVE MONITORING ..................................................................................................................... 142 4.6 T1/E1 SERIAL PCM INTERFACE ................................................................................................................... 143 4.7 T1/E1 FRACTIONAL INTERFACE .................................................................................................................. 144 4.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL ..................................................................................... 145 4.9 ROBBED BIT SIGNALING/CAS SIGNALING ................................................................................................. 146 4.10 OVERHEAD INTERFACE .............................................................................................................................. 148 4.11 FRAMER BYPASS MODE ............................................................................................................................. 149 4.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE ........................................................................................ 150 4.13 HIGH-SPEED MULTIPLEXED INTERFACE ................................................................................................. 151 5.0 LOOPBACK MODES OF OPERATION ...............................................................................................152 5.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS ............................................................................ 152 5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 152 5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 152 5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 153 5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 153 5.1.5 FRAMER REMOTE LINE LOOPBACK ...................................................................................................................... 153 5.1.6 FRAMER PAYLOAD LOOPBACK ............................................................................................................................. 154 5.1.7 FRAMER LOCAL LOOPBACK ................................................................................................................................... 154 6.0 HDLC CONTROLLERS AND LAPD MESSAGES ...............................................................................155 6.1 PROGRAMMING SEQUENCE FOR SENDING LESS THAN 96-BYTE MESSAGES .................................... 155 6.2 PROGRAMMING SEQUENCE FOR SENDING LARGE MESSAGES ........................................................... 155 6.3 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES ........................................................... 156 6.4 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY ................................................................ 156 6.5 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS ................................................. 157 6.6 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR ..................................................................... 157 6.6.1 DESCRIPTION OF BOS .............................................................................................................................................. 157 6.6.2 PRIORITY CODEWORD MESSAGE .......................................................................................................................... 157 6.6.3 COMMAND AND RESPONSE INFORMATION .......................................................................................................... 157 6.7 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR ........................................................ 158 6.7.1 DISCUSSION OF MOS ............................................................................................................................................... 158 6.7.2 PERIODIC PERFORMANCE REPORT ...................................................................................................................... 158 6.7.3 TRANSMISSION-ERROR EVENT .............................................................................................................................. 159 6.7.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ......................................................................................... 159 6.7.5 FRAME STRUCTURE ................................................................................................................................................. 159 6.7.6 FLAG SEQUENCE ...................................................................................................................................................... 159 6.7.7 ADDRESS FIELD ........................................................................................................................................................ 160 6.7.8 ADDRESS FIELD EXTENSION BIT (EA) ................................................................................................................... 160 |
Similar Part No. - XRT86L30_07 |
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Similar Description - XRT86L30_07 |
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