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XRT86L30 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT86L30 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 279 page XRT86L30 II REV. 1.0.0 SINGLE T1/E1/J1 FRAMER/LIU COMBO 6.7.9 COMMAND OR RESPONSE BIT (C/R) ...................................................................................................................... 160 6.7.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ...................................................................................................... 160 6.7.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ............................................................................................................... 160 6.7.12 CONTROL FIELD ...................................................................................................................................................... 160 6.7.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................. 160 6.7.14 TRANSPARENCY (ZERO STUFFING) ..................................................................................................................... 161 6.8 TRANSMIT SLC®96 DATA LINK CONTROLLER .......................................................................................... 162 6.9 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................ 163 6.10 AUTOMATIC PERFORMANCE REPORT (APR) .......................................................................................... 163 6.10.1 BIT VALUE INTERPRETATION ............................................................................................................................... 163 7.0 OVERHEAD INTERFACE BLOCK ...................................................................................................... 165 7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .......................................................................... 165 7.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................. 165 7.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ............................................................................................... 165 7.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 167 7.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG- NALING (R) BITS IN T1DM FRAMING FORMAT MODE ........................................................................................... 168 7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 168 7.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................. 169 7.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE .................................................................................... 169 7.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 170 7.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ..................................................................................... 171 7.3 E1 OVERHEAD INTERFACE BLOCK ............................................................................................................ 172 7.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 172 7.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................. 172 7.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE- QUENCE IN E1 FRAMING FORMAT MODE .............................................................................................................. 173 7.5 E1 RECEIVE OVERHEAD INTERFACE ......................................................................................................... 175 7.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 175 7.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SEQUENCE IN E1 FRAMING FORMAT MODE .......................................................................................................... 176 8.0 LIU TRANSMIT PATH ......................................................................................................................... 178 8.1 TRANSMIT DIAGNOSTIC FEATURES ........................................................................................................... 178 8.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................. 178 8.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ......................................................................................................... 179 8.1.3 NETWORK LOOP UP CODE ...................................................................................................................................... 179 8.1.4 NETWORK LOOP DOWN CODE ............................................................................................................................... 179 8.1.5 QRSS GENERATION .................................................................................................................................................. 180 8.2 T1 LONG HAUL LINE BUILD OUT (LBO) ...................................................................................................... 180 8.3 T1 SHORT HAUL LINE BUILD OUT (LBO) .................................................................................................... 181 8.3.1 ARBITRARY PULSE GENERATOR ........................................................................................................................... 181 8.3.2 DMO (DIGITAL MONITOR OUTPUT) ......................................................................................................................... 182 8.3.3 TRANSMIT JITTER ATTENUATOR ........................................................................................................................... 182 8.4 LINE TERMINATION (TTIP/TRING) ................................................................................................................ 183 9.0 LIU RECEIVE PATH ............................................................................................................................ 184 9.1 LINE TERMINATION (RTIP/RRING) ............................................................................................................... 184 9.1.1 CASE 1: INTERNAL TERMINATION .......................................................................................................................... 184 9.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 184 9.1.3 EQUALIZER CONTROL ............................................................................................................................................. 185 9.1.4 CABLE LOSS INDICATOR ......................................................................................................................................... 185 9.2 RECEIVE SENSITIVITY ................................................................................................................................... 186 9.2.1 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 186 9.2.2 NLCD (NETWORK LOOP CODE DETECTION) ......................................................................................................... 186 9.2.3 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 187 9.2.4 RECEIVE JITTER ATTENUATOR .............................................................................................................................. 187 9.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 187 10.0 THE E1 TRANSMIT/RECEIVE FRAMER .......................................................................................... 189 10.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK ................ 189 10.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT |
Similar Part No. - XRT86L30_07 |
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Similar Description - XRT86L30_07 |
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