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XRT86L30 Datasheet(PDF) 11 Page - Exar Corporation

Part # XRT86L30
Description  SINGLE T1/E1/J1 FRAMER/LIU COMBO
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86L30 Datasheet(HTML) 11 Page - Exar Corporation

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XRT86L30
VIII
REV. 1.0.0
SINGLE T1/E1/J1 FRAMER/LIU COMBO
LIST OF TABLES
Table 1:: List by Pin Number ............................................................................................................................................. 4
Table 2:: Selecting the Microprocessor Interface Mode .................................................................................................. 18
Table 3:: XRT86L30 Microprocessor Interface Signals that exhibit constant roles in both Intel and Motorola Modes .... 19
Table 4:: Intel mode: Microprocessor Interface Signals ................................................................................................... 19
Table 5:: Motorola Mode: Microprocessor Interface Signals ........................................................................................... 20
Table 6:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 22
Table 7:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 24
Table 8:: Motorola 68K Microprocessor Interface Timing Specifications ......................................................................... 25
Table 9:: XRT86L30 Framer/LIU Register Map ............................................................................................................... 27
Table 10:: Register Summary .......................................................................................................................................... 28
Table 11:: Clock Select Register E1 Mode ...................................................................................................................... 34
Table 12:: Line Interface Control Register T1 Mode ........................................................................................................ 35
Table 13:: General Purpose Input/Output 0 Control Register .......................................................................................... 35
Table 14:: Framing Select Register-E1 Mode .................................................................................................................. 36
Table 15:: Framing Select Register-T1 Mode .................................................................................................................. 37
Table 16:: Alarm Generation Register - E1 Mode ............................................................................................................ 38
Table 17:: Alarm Generation Register -T1 Mode ............................................................................................................. 39
Table 18:: Synchronization MUX Register - E1 Mode ..................................................................................................... 41
Table 19:: Synchronization MUX Register - T1 Mode ..................................................................................................... 42
Table 20:: Transmit Signaling and Data Link Select Register - E1 Mode ........................................................................ 43
Table 21:: Transmit Signaling and Data Link Select Register - T1 Mode ........................................................................ 44
Table 22:: Framing Control Register E1 Mode ................................................................................................................ 45
Table 23:: Framing Control Register T1 Mode ................................................................................................................ 46
Table 24:: Receive Signaling & Data Link Select Register - E1 Mode ............................................................................ 47
Table 25:: Receive Signaling & Data Link Select Register (RS&DLSR) T1 Mode .......................................................... 48
Table 26:: Signaling Change Register 0 - T1 Mode ......................................................................................................... 49
Table 27:: Signaling Change Register 1 .......................................................................................................................... 49
Table 28:: Signaling Change Register 2 .......................................................................................................................... 50
Table 29:: Signaling Change Register 3 .......................................................................................................................... 50
Table 30:: Receive National Bits Register ....................................................................................................................... 50
Table 31:: Receive Extra Bits Register ............................................................................................................................ 51
Table 32:: Data Link Control Register .............................................................................................................................. 52
Table 33:: Transmit Data Link Byte Count Register ........................................................................................................ 53
Table 34:: Receive Data Link Byte Count Register ......................................................................................................... 54
Table 35:: Slip Buffer Control Register ............................................................................................................................ 54
Table 36:: FIFO Latency Register .................................................................................................................................... 55
Table 37:: DMA 0 (Write) Configuration Register ............................................................................................................ 55
Table 38:: DMA 1 (Read) Configuration Register ............................................................................................................ 56
Table 39:: Interrupt Control Register ............................................................................................................................... 57
Table 40:: LAPD Select Register ..................................................................................................................................... 57
Table 41:: Customer Installation Alarm Generation Register .......................................................................................... 58
Table 42:: Performance Report Control Register ............................................................................................................ 58
Table 43:: Gapped Clock Control Register ...................................................................................................................... 59
Table 44:: Gapped Clock Control Register ...................................................................................................................... 59
Table 45:: Transmit Interface Control Register - E1 Mode .............................................................................................. 60
Table 46:: Transmit Interface Control Register - T1 Mode .............................................................................................. 61
Table 47:: Receive Interface Control Register (RICR) - E1 Mode ................................................................................... 63
Table 48:: Receive Interface Control Register (RICR) - T1 Mode ................................................................................... 64
Table 49:: DS1 Test Register .......................................................................................................................................... 65
Table 50:: Loopback Code Control Register .................................................................................................................... 66
Table 51:: Transmit Loopback Coder Register ................................................................................................................ 67
Table 52:: Receive Loopback Activation Code Register .................................................................................................. 67
Table 53:: Receive Loopback Deactivation Code Register ............................................................................................. 67
Table 54:: Transmit Sa Select Register ........................................................................................................................... 68
Table 55:: Transmit Sa Auto Control Register 1 .............................................................................................................. 68
Table 56:: Conditions on Receive side When TSACR1 bits Are enabled ........................................................................ 69
Table 57:: Transmit Sa Auto Control Register 2 .............................................................................................................. 69
Table 58:: Conditions on Receive side When TSACR1 bits enabled .............................................................................. 70


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