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XRT86L30 Datasheet(PDF) 8 Page - Exar Corporation

Part # XRT86L30
Description  SINGLE T1/E1/J1 FRAMER/LIU COMBO
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86L30 Datasheet(HTML) 8 Page - Exar Corporation

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XRT86L30
V
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.0
LIST OF FIGURES
Figure 1.: XRT86L30 1-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................... 1
Figure 2.: Simplified Block Diagram of the Microprocessor Interface Block .................................................................... 18
Figure 3.: Intel µP Interface Signals During Programmed I/O Read and Write Operations ............................................. 22
Figure 4.: Motorola µP Interface Signals During Programmed I/O Read and Write Operations ...................................... 24
Figure 5.: Motorola 68K µP Interface Signals During Programmed I/O Read and Write Operations .............................. 25
Figure 6.: DMA Mode for the XRT86L30 and a Microprocessor ...................................................................................... 26
Figure 7.: LIU Transmit Connection Diagram Using Internal Termination ..................................................................... 139
Figure 8.: LIU Receive Connection Diagram Using Internal Termination ..................................................................... 139
Figure 9.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ........................................ 140
Figure 10.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy .......................................141
Figure 11.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ........................................................... 142
Figure 12.: Transmit T1/E1 Serial PCM Interface .......................................................................................................... 143
Figure 13.: Receive T1/E1 Serial PCM Interface ........................................................................................................... 143
Figure 14.: T1 Fractional Interface ................................................................................................................................. 144
Figure 15.: T1/E1 Time Slot Substitution and Control .................................................................................................... 145
Figure 16.: Robbed Bit Signaling / CAS Signaling ......................................................................................................... 146
Figure 17.: ESF / CAS External Signaling Bus .............................................................................................................. 146
Figure 18.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus ...................................................... 147
Figure 19.: T1/E1 Overhead Interface ........................................................................................................................... 148
Figure 20.: T1 External Overhead Datalink Bus ............................................................................................................ 148
Figure 21.: E1 Overhead External Datalink Bus ............................................................................................................ 149
Figure 22.: Simplified Block Diagram of the Framer Bypass Mode ............................................................................... 149
Figure 23.: T1 High-Speed Non-Multiplexed Interface ................................................................................................... 150
Figure 24.: E1 High-Speed Non-Multiplexed Interface .................................................................................................. 150
Figure 25.: Transmit High-Speed Bit Multiplexed Block Diagram .................................................................................. 151
Figure 26.: Receive High-Speed Bit Multiplexed Block Diagram ................................................................................... 151
Figure 27.: Simplified Block Diagram of Local Analog Loopback .................................................................................. 152
Figure 28.: Simplified Block Diagram of Remote Loopback ........................................................................................... 152
Figure 29.: Simplified Block Diagram of Digital Loopback ............................................................................................. 153
Figure 30.: Simplified Block Diagram of Dual Loopback ................................................................................................ 153
Figure 31.: Simplified Block Diagram of the Framer Remote Line Loopback ................................................................ 153
Figure 32.: Simplified Block Diagram of the Framer Local Loopback ............................................................................ 154
Figure 33.: Simplified Block Diagram of the Framer Local Loopback ............................................................................ 154
Figure 34.: HDLC Controllers ......................................................................................................................................... 155
Figure 35.: LAPD Frame Structure ................................................................................................................................ 158
Figure 36.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86L30 ....................................... 165
Figure 37.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode .......................................... 167
Figure 38.: DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode .......................................... 168
Figure 39.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ...................................... 168
Figure 40.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86L30 ............................................ 169
Figure 41.: DS1 Receive Overhead Output Interface module in ESF framing format mode ......................................... 170
Figure 42.: DS1 Receive Overhead Output Interface Timing in N or SLC®96 Framing Format mode .......................... 171
Figure 43.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode ..................................... 172
Figure 44.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86L30 ................................................ 173
Figure 45.: E1 Transmit Overhead Input Interface Timing ............................................................................................. 175
Figure 46.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86L30 ..............................................175
Figure 47.: E1 Receive Overhead Output Interface Timing ........................................................................................... 177
Figure 48.: TAOS (Transmit All Ones) ........................................................................................................................... 178
Figure 49.: Simplified Block Diagram of the ATAOS Function ....................................................................................... 179
Figure 50.: Network Loop Up Code Generation ............................................................................................................. 179
Figure 51.: Network Loop Down Code Generation ........................................................................................................ 179
Figure 52.: Long Haul Line Build Out with -7.5dB Attenuation ....................................................................................... 180
Figure 53.: Long Haul Line Build Out with -15dB Attenuation ........................................................................................ 180
Figure 54.: Long Haul Line Build Out with -22.5dB Attenuation ..................................................................................... 181
Figure 55.: Arbitrary Pulse Segment Assignment .......................................................................................................... 182
Figure 56.: Typical Connection Diagram Using Internal Termination ............................................................................ 183
Figure 57.: Typical Connection Diagram Using Internal Termination ........................................................................... 184
Figure 58.: Typical Connection Diagram Using One External Fixed Resistor ............................................................... 185


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