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XRT86SH328 Datasheet(PDF) 2 Page - Exar Corporation

Part # XRT86SH328
Description  28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET
Download  339 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86SH328 Datasheet(HTML) 2 Page - Exar Corporation

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XRT86SH328
PRELIMINARY
2
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS REV. P1.0.6
FIGURE 1. BLOCK DIAGRAM OF THE XRT86SH328
TABLE 1: ORDERING INFORMATION
PRODUCT NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRT86SH328IB
568 Ball BGA
-40°C to +85°C
ST S-1/
ST S-3
T elecom
Bus
Interface
ST S-1/
ST S-3
T elecom
Bus
Interface
Transm it
ST S-1/3
TO H
Processor
Block
Transm it
ST S-1/3
TO H
P rocessor
Block
R eceive
ST S-1/3
TO H
Processor
Block
R eceive
ST S-1/3
TO H
Processor
Block
Transm it
ST S-1 PO H
Processor
Block
Transm it
ST S-1 P O H
Processor
Block
R eceive
ST S-1 P O H
Processor
Block
R eceive
ST S-1 P O H
P rocessor
Block
VT /T U
D e-M apper
Block
R eceive
DS3
Fram er
Block
Receive
DS3
Fram er
Block
Transm it
DS3
Fram er
Block
Transm it
DS3
Fram er
Block
M23
MU X
Block
M23
MU X
Block
M23
De-M UX
Block
M23
De-M UX
Block
Ingress
D irection
Receive
DS1/E 1
Fram er
Block
Egress
D irection
R eceive
DS1/E 1
Fram er
Block
Ingress
Direction
Transm it
DS1/E1
Fram er
Block
Egress
D irection
Transm it
DS1/E 1
Fram er
Block
Receive
DS1/E 1
LIU
Block
Transm it
DS1/E 1
LIU
Block
DS3/
ST S-1
LIU
Interface
DS3/
ST S-1
LIU
Interface
M12
MU X
Block
M12
De-M UX
Block
DS1/E 1
Jitter
Atten
Block
DS1/E1 Channel 0
DS1/E1 Channel 0
DS2 Channel 0
F rom D S1/E 1 C hannels 1 - 27
F rom D S2 C hannels 1 - 6
T o D S2 C hannels 1 - 6
F rom D S1/E 1 C hannels 1 - 3
T o DS1/E1 Channels 1 - 3
To D S1/E 1
C hannels 1 - 27
VT/T U
Mapper
Block
VT /T U
Mapper
Block
DS2 Channel 0
ST S-1/
ST S-3
T elecom
Bus
Interface
ST S-1/
ST S-3
T elecom
Bus
Interface
Transm it
ST S-1/3
TO H
Processor
Block
Transm it
ST S-1/3
TO H
P rocessor
Block
R eceive
ST S-1/3
TO H
Processor
Block
R eceive
ST S-1/3
TO H
Processor
Block
Transm it
ST S-1 PO H
Processor
Block
Transm it
ST S-1 P O H
Processor
Block
R eceive
ST S-1 P O H
Processor
Block
R eceive
ST S-1 P O H
P rocessor
Block
VT /T U
D e-M apper
Block
R eceive
DS3
Fram er
Block
Receive
DS3
Fram er
Block
Transm it
DS3
Fram er
Block
Transm it
DS3
Fram er
Block
M23
MU X
Block
M23
MU X
Block
M23
De-M UX
Block
M23
De-M UX
Block
Ingress
D irection
Receive
DS1/E 1
Fram er
Block
Egress
D irection
R eceive
DS1/E 1
Fram er
Block
Ingress
Direction
Transm it
DS1/E1
Fram er
Block
Egress
D irection
Transm it
DS1/E 1
Fram er
Block
Receive
DS1/E 1
LIU
Block
Transm it
DS1/E 1
LIU
Block
DS3/
ST S-1
LIU
Interface
DS3/
ST S-1
LIU
Interface
M12
MU X
Block
M12
De-M UX
Block
DS1/E 1
Jitter
Atten
Block
DS1/E1 Channel 0
DS1/E1 Channel 0
DS2 Channel 0
F rom D S1/E 1 C hannels 1 - 27
F rom D S2 C hannels 1 - 6
T o D S2 C hannels 1 - 6
F rom D S1/E 1 C hannels 1 - 3
T o DS1/E1 Channels 1 - 3
To D S1/E 1
C hannels 1 - 27
VT/T U
Mapper
Block
VT /T U
Mapper
Block
DS2 Channel 0


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