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XRT94L33 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT94L33 Datasheet(HTML) 5 Page - Exar Corporation |
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5 / 110 page  XRT94L33 Rev 2 22 ...0 00 ...0 00 3 33 ---C C C H H H A A AN N N N N N E E E L L L D D D S S S 3 33 ///E E E 3 33 ///S S S T T T S S S - -- 1 11 T T T O O O S S S T T T S S S - -- 3 33 ///S S S T T T M M M - -- 1 11 M M M A A AP P P P P P E E E R R R S S S O O O N N N E E E T T T A A AT T T M M M ///P P P P P P P P P – –– H H H A A AR R R W W W A A A R R R E E E M M M A A AN N N U U U A A AL L L 5 PIN # SIGNAL NAME I/O SIGNAL TYPE DESCRIPTION AF22 PWR_L/ R/W* I TTL Write Strobe/Read-Write Operation Identifier: The exact function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode – WR* - Write Strobe Input: If the Microprocessor Interface is configured to operate in the Intel-Asynchronous Mode, then this input pin functions as the WR* (Active-Low WRITE Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the input buffers (associated with the Bi-Directional Data Bus pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the “target” register or address location, within the XRT94L33) upon the rising of this input. Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identification Input Pin: If the Microprocessor Interface is operating in the “Motorola- Asynchronous” Mode, then this pin is functionally equivalent to the “R/W*” input pin. In the Motorola Mode, a “READ” operation occurs if this pin is held at a logic “1”, coincident to a falling edge of the RD/DS* (Data Strobe) input pin. PowerPC 403 Mode – R/W* - Read/Write Operation Identification Input: If the Microprocessor Interface is configured to operate in the PowerPC 403 Mode, then this input pin will function as the “Read/Write Operation Identification” input pin. Anytime the Microprocessor Interface samples this input signal at a logic “low” (while also sampling the CS* input pin “low”) upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A]14:0]) into the Microprocessor Interface circuitry, in preparation for this forthcoming READ operation. At some point (later in this READ operation) the Microprocessor will also assert the DBEN*/OE* input pin, and the Microprocessor Interface will then place the contents of the “target” register (or address location within the XRT94L33) upon the Bi-Directional Dat Bus pins (D[7:0]), where it can be read by the Microprocessor. Anytime the Microprocessor Interface samples this input signal at a logic high (while also sampling the CS* input pin at a logic “low”) upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in preparation for the forthcoming WRITE operation. At some point (later in this WRITE operation) the Microprocessor will also assert the RD*/DS*/WE* input pin, and the Microprocessor Interface will then latch the contents of the Bi-Directional Data Bus (D[7:0]) into the contents of the “target” register or buffer location (within the XRT94L33). |
Similar Part No. - XRT94L33 |
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Similar Description - XRT94L33 |
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