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XRT94L33 Datasheet(PDF) 9 Page - Exar Corporation |
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XRT94L33 Datasheet(HTML) 9 Page - Exar Corporation |
9 / 110 page XRT94L33 Rev 2 22 ...0 00 ...0 00 3 33 ---C C C H H H A A AN N N N N N E E E L L L D D D S S S 3 33 ///E E E 3 33 ///S S S T T T S S S - -- 1 11 T T T O O O S S S T T T S S S - -- 3 33 ///S S S T T T M M M - -- 1 11 M M M A A AP P P P P P E E E R R R S S S O O O N N N E E E T T T A A AT T T M M M ///P P P P P P P P P – –– H H H A A AR R R W W W A A A R R R E E E M M M A A AN N N U U U A A AL L L 9 PIN # SIGNAL NAME I/O SIGNAL TYPE DESCRIPTION AF21 PDBEN_L I TTL Bi-directional Data Bus Enable Input pin: This input pin permits the user to either enable or tri-state the Bi- Directional Data Bus pins (D[7:0]), as described below. Setting this input pin “low” enables the Bi-directional Data bus. Setting this input “high” tri-states the Bi-directional Data Bus. AF20 PBLAST_L I TTL Last Burst Transfer Indicator input pin: If the Microprocessor Interface is operating in the Intel-I960 Mode, then this input pin is used to indicate (to the Microprocessor Interface block) that the current data transfer is the last data transfer within the current burst operation. The Microprocessor should assert this input pin (by toggling it “Low”) in order to denote that the current READ or WRITE operation (within a BURST operation) is the last operation of this BURST operation. Note: The user should connect this input pin to GND whenever the Microprocessor Interface has been configured to operate in the Intel-Async, Motorola 68K and IBM PowerPC 403 modes. AG22 PINT_L O CMOS Interrupt Request Output: This open-drain, active-low output signal will be asserted when the Mapper/Framer device is requesting interrupt service from the Microprocessor. This output pin should typically be connected to the “Interrupt Request” input of the Microprocessor. AB24 RESET_L I TTL Reset Input: When this “active-low” signal is asserted, the XRT94L33 will be asynchronously reset. When this occurs, all outputs will be “tri- stated” and all on-chip registers will be reset to their “default” values. AE18 DIRECT_ADD_SEL I TTL Address Location Select input pin: This input pin must be pulled “HIGH” in order to permit normal operation of the Microprocessor Interface. SONET/SDH SERIAL LINE INTERFACE PINS T3 RXLDAT_P I LVPECL Receive STS-3/STM-1 Data – Positive Polarity PECL Input: This input pin, along with RXLDAT_N functions as the Recovered Data Input, from the Optical Transceiver or as the Receive Data Input from the system back-plane Note: For APS (Automatic Protection Switching) purposes, this input pin, along with “RXLDAT_N” functions as the “Primary” STS-3/STM-1 Receive Data Input Port. T2 RXLDAT_N I LVPECL Receive STS-3/STM-1 Data – Negative Polarity PECL Input: This input pin, along with RXLDAT_P functions as the Recovered Data Input, from the Optical Transceiver or as the Receive Data Input from the system back-plane. Note: For APS (Automatic Protection Switching) purposes, this input pin, along with “RXLDAT_P” functions as the “Primary Receive STS-3/STM-1 Data Input Port” |
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