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XRT94L33IB Datasheet(PDF) 8 Page - Exar Corporation |
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XRT94L33IB Datasheet(HTML) 8 Page - Exar Corporation |
8 / 110 page XRT94L33 3 33 ---C C C H H H A A AN N N N N N E E E L L L D D D S S S 3 33 ///E E E 3 33 ///S S S T T T S S S - -- 1 11 T T T O O O S S S T T T S S S - -- 3 33 ///S S S T T T M M M - -- 1 11 M M M A A AP P P P P P E E E R R R S S S O O O N N N E E E T T T A A AT T T M M M ///P P P P P P P P P – –– H H H A A AR R R W W W A A A R R R E E E M M M A A AN N N U U U A A AL L L Rev 2 22 ...0 00 ...0 00 8 PIN # SIGNAL NAME I/O SIGNAL TYPE DESCRIPTION AD18 PRDY_L/ DTACK* RDY O CMOS READY or DTACK Output: The exact function of this input pin depends upon wich mode the Microprocessor Interface has been configured to operate in, as described below. Intel Asynchronous Mode – RDY* - READY output: If the Microprocessor Interface has been configured to operate in the Intel-Asyncrhronous Mode, then this output pin will function as the “active-low” READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic “low” level ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic “low” level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic “high” level, then the MIcroprocessor is expected to extend this READ or WRITE cycle, until it detect this output pin being toggled to the logic low level. Motorola Mode – DTACK* - Data Transfer Acknowledge Output: If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then this output pin will function as the “active-low” DTACK* ouytput. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic “low” leve, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic “high” level, then the MIcroprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level. PowerPC 403 Mode – RDY – Ready Output: If the Microprocessor Interface has been configured to operate in the PowerPC 403 Mode, then this output pin will function as the “active-high” READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic high level, ONLY when it (the Microprocessor Interface) is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has sampled this signal being at a logic “high” level (upon the rising edge of PCLK) then it is now safe for it to move on and execute the next READ or WRITE cycle. The Microprocessor Interface will update the state of this output pin upon the rising edge of PCLK. |
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