Philips Semiconductors RF Communications Products

Product specification

SA702

Divide by: 64/65/72 triple modulus low power

ECL prescaler

June 17, 1993

4

DC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

Power supply voltage range

2.7

6.0

V

Supply current

No load

4.5

mA

Output high level

V

Output low level

V

MC1 input high threshold

2.0

V

MC1 input low threshold

–0.3

0.8

V

MC2 input high threshold

2.0

V

MC2 input low threshold

–0.3

0.8

V

MC1 input high current

0.1

50

µA

MC1 input low current

–100

–30

µA

MC2 input high current

0.1

50

µA

MC2 input low current

–100

–30

µA

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

MIN

TYP

MAX

1000pF input coupling

0.05

2.0

Input signal frequency

0

1.1

GHz

1000pF input coupling

1.1

GHz

Differential input resistance

DC measurement

5

k

Ω

Output voltage

1.6

1.2

5

ns

0

ns

Propagation time

10

ns

NOTES:

1. Maximum limit is not tested, however, it is guaranteed by design and characterization.

DESCRIPTION OF OPERATION

The SA702 comprises a frequency divider

circuit implemented using a divide by 4 or 5

synchronous prescaler followed by a 5 stage

synchronous counter, see BLOCK

DIAGRAM. The normal operating mode is for

MC1 (Modulus Control) to be set high and

MC2 input to be set low in which case the

circuit comprises a divide by 64. For divide

by 65 the MC1 singal is forced low, causing

the prescaler circuit to switch into divide by 5

operation for the last cycle of the

synchronous counter. For divide by 72, MC2

is set high configuring the prescaler to divide

by 4 and the counter to divide by 18. A truth

table for the modulus values is given below:

Table 1.

Modulus

MC1

MC2

64

1

0

65

0

0

72

0

1

72

1

1

For minimization of propagation delay effects,

the second divider circuit is synchronous to

the divide by 4/5 stage output.

The prescaler input is positive edge sensitive,

and the output at the final count is a falling

the input. The rising edge of the output

The MC1 and MC2 inputs are TTL

compatible threshold inputs operating at a

reduced input current. CMOS and low

voltage interface capability are allowed.

The prescaler input is differential and ECL

compatible. The output is differential ECL

compatible.