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XRT94L43IB Datasheet(PDF) 5 Page - Exar Corporation |
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XRT94L43IB Datasheet(HTML) 5 Page - Exar Corporation |
5 / 328 page XRT94L43 5 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER REV. 1.0.2 • Contains 12 on-chip 64 byte Expected Receive Path Trace Message Buffer, in which the user will load in an expected Path Trace Message • Contains 12 on-chip 64 byte Actual" Receive Path Trace Message Buffers, that will contain the actual Received Path Trace Message • The SONET Receiver will use the contents within both the Expected and Actual Receive Path Trace Message Buffers to either declare or clear the TIM-P defect condition • Computes and verifies the B3 bytes within each incoming STS-1 SPE/VC-3 or STS-3c SPE/VC-4 and increments on-chip Performance Monitoring registers each time it detects B3 byte errors. • Detects and Flags Line - Remote Error Indicator (REI-L) and Path - Remote Error Indicator (REI-P) events, and increments on-chip Performance Monitoring registers each time it detects REI-L or REI-P events • Computes and verifies both the B1 and B2 bytes within the incoming STS-12/STM-4 data-stream and increments on-chip Performance Monitoring registers each time it detects B1 or B2 byte errors MAPPER • Maps DS3 data into/De-maps DS3 data from an STS-1 SPE per the requirements in Telcordia GR-253- CORE • Maps DS3/E3 data into/De-Maps DS3/E3 data from a VC-3 per ITU-T G.707 • Implements AU-3 to VC-3 multiplexing and de-multiplexing DS3 RECEIVE FRAMER • Offers off-line framing algorithm • Complies with the standards as: Bellcore TR-NWT-000499 and TR-NWT-000009 • Supports overhead extraction • Detects and flags LCV (Line Code Violations) and EXZ (Excessive Zero Events). • Reports and counts FEBE • HDLC controller complies with ITU-T Q.921 LAPD protocol • Provides Line and Local Loop-backs • Supports either the M13 or the C-bit Parity Framing formats • Supports B3ZS line decoding which can be user enabled.Replaces valid B0V or 00V with 3 zeros • Synchronizes to incoming frame based upon 10 valid F bits followed by 3 consecutive valid M frames, Offers optional AIC-bit or parity verification before declaration of sync • Detects Out of Frame (OOF) upon 3 or 6 F bits out of 15 F bits in error or 1 or more M bits in 3 of 4 consecutive frames in error • Detects Loss of Signal (LOS) upon encountering 180 consecutive 0’s and clears on at least 60 of successive received 1’s.Offers optional disable • Detects idle state by checking C-bit in subframe 3 are all zero, X-bits are one and repeating 11001100 payloads. Declaration occurs when all the above conditions persist for 63 M-frames. Clears the condition when 63 valid M-frames are received • Detects AIS with different algorithm • Computes and verifies P and CP-Bits • Validate FERF bits, sets to one when both X-bits are zero and clears when they are One • Detects and validates FEAC codes upon 8 out of 10 last identical received codes.Invalidates on 3 in 10 mismatch |
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