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XR68C192CV Datasheet(PDF) 10 Page - Exar Corporation |
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XR68C192CV Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 33 page  XR68C92/192 10 Rev. 1.33 A start-break is deferred as long as the transmitter has characters to send, but if normal character transmis- sion is inhibited by CTS, the start-break will proceed. The start-break must be terminated by a stop-break or a TX disable + TX reset before normal character transmission can resume. The channel A and B transmitters are enabled for data transmission through their respective command regis- ters (see CRA, CRB bits 3:2). The transmit FIFO trigger levels (see MR0A, MR0B bits 4 and 5) are used to generate an interrupt request to the CPU on the -INT pin. This is also reflected in the Interrupt Status Regis- ter, ISR bit-0 for channel A and bit-4 for channel B. This is different from the TxRDY bit in the status register. The TxRDY bit in the status register (SRA, SRB bit-2) indicates if the TX FIFO has at least one empty location. This can also be programmed to appear at the output pin OP6/OP7. The TxEMT bit (SRA, SRB bit-3) indicates if both the TX FIFO and the TX Shift Register are empty. The transmitter can be reset through a software com- mand (CRA, CRB bits 7:4). If it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. Reset also discards any characters in the FIFO. RECEIVER The channel A and B receivers are enabled for data reception through the respective channels command register (CRA, CRB bits 1:0). The channels receiver looks for the high-to-low (mark-to-space) transition of a start bit on the receiver serial-data input pin. If operating in 16X clock mode, the serial input data is re- sampled on the next 7 clocks. If the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. If receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been assembled and one stop bit has been detected. If an 1X clock is used, data is sampled at one bit time intervals throughout, including the start bit. Data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source (XTAL1, IP4 or IP6: see CSR bits 7:4). In this process, the least significant bit is received first. The receiver buffer is composed of the FIFO (8/16 locations in XR68C92/192 respectively) and a receive shift register connected to the receiver serial-data input. Data is assembled in the shift register and loaded into the bottom most empty FIFO location. If the character length is less than eight bits, the most significant unused bits are set to zero. If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit. However, if the stop bit is sampled as a 0, either a framing error or a received break has occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing error. The damaged character is transferred to the FIFO with the framing error flag set. If the receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. If the stop bit is 0 and the data and parity (if any) bits are also all zero, it is a break. A character consisting of all zeros will be loaded into the the FIFO with the received-break bit (but not the framing error bit) set to one. The receiver serial-data input must return to a high condition for at least one-half bit time before a search for the next start bit begins. Also, at this time, the received break bit is reset. The receiver can detect a break that starts in the middle of a character provided the break persists completely through the next character time or longer. When the break begins in the middle of a character, the receiver will place the damaged character in the FIFO with the framing error bit set. Then, provided the break persists through the next character time, the receiver will also place an all-zero character in the FIFO with the re- ceived-break bit set. The parity error, framing error, overrun error, and received-break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver-ready bit (RXRDY) in the status register is set. The receiver-ready bit in the status register (SRA, SRB bit-0) is set whenever one or more characters are available to be read by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are “popped” and new data can be added at the bottom of the stack by the receive shift register. The FIFO-full status bit (SRA, SRB bit-1) is set if all 8 (or 16) stack positions are filled with data. Either the receiver-ready |
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