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SAA2502H Datasheet(PDF) 7 Page - NXP Semiconductors |
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SAA2502H Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 64 page  1997 Nov 17 7 Philips Semiconductors Preliminary specification ISO/MPEG Audio Source Decoder SAA2502 7 FUNCTIONAL DESCRIPTION 7.1 Basic functionality From a functional point of view, several blocks can be distinguished in the SAA2502. A clock generator section derives the internally and externally required clock signals from its clock inputs. The input interface section receives or requests coded input data in one of the supported input interface modes. The demultiplexer processor handles frame synchronization, parsing, demultiplexing and error concealment of the input data stream The de-quantization and scaling processor performs the transformation and scaling operations on the (demultiplexed) coded sample representations in the input bitstream to yield sub-band domain samples. The sub-band samples are transferred to the synthesis sub-band filter bank processor which reconstructs the baseband audio samples. The output interface block transforms the audio samples to the output formats required by the different output ports. The decoding control block houses the I2C-bus/L3 microcontroller interface, and handles the response to external control signals. This section enables the application to configure the SAA2502, to read its decoding status, to read ancillary data and so on. Several pins are reserved for boundary scan test (5 pins) and factory test scan chain control (2 pins). 7.2 Clock generator module The SAA2502 clock interfacing is designed for application versatility. It consists of 9 signals (see Table 1). The clock generator provides the following clock signals: • Internal sample clocks • External buffered sample clock FSCLK • Processor master clock • Coded input data bit clock • Coded input data request clock The module can be configured to operate in 3 different modes of operation: • External sample clock mode • Free running internal sample clock mode • Locked internal sample clock mode. Clock generator operation mode must be stationary while the device is in normal operation. Changing mode should always be followed by a (soft) reset. f input bit rate 32 ----------------------------------- = Table 1 Clock interfacing signals SIGNAL DIRECTION FUNCTION MCLKIN input master clock oscillator input or signal input MCLKOUT output master clock oscillator output MCLK24 input master clock frequency indication X22IN input 22.5792 MHz clock oscillator input or signal input X22OUT output 22.5792 MHz clock oscillator output FSCLKIN input external sample rate clock signal input FSCLK output sample rate clock signal output REFCLK input coded input data rate reference clock PHDIF output phase difference indication output between reference clock and sample clock |
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