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SAA2520GP Datasheet(PDF) 4 Page - NXP Semiconductors |
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SAA2520GP Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 36 page August 1993 4 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 PINNING SYMBOL PIN DESCRIPTION TYPE FS256 1 (Filtered)-I2S clock; 256 × sample frequency. 12 mA 3-state output + CMOS input with pull-down I/O MUTEDAC 2 DAC control/output expander O DEEMDAC 3 DAC control/output expander O ATTDAC 4 DAC control/output expander O VSS 5 supply ground (0 V) URDA 6 unreliable drive processing data; CMOS level I SBDIR 7 sub-band I2S direction: (SWBS, SBCL, SBDA); CMOS level I SBDA 8 sub-band I2S data; 4 mA, 3-state output + CMOS input with pull-down I/O SBCL 9 sub-band I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O SBWS 10 sub-band I2S word select; 4 mA, 3-state output + CMOS input with pull-down I/O SBEF 11 sub-band I2S byte error flag; CMOS level I SBMCLK 12 sub-band I2S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS input with pull-down O SYNCDAI 13 DAI synchronization pulse O FDIR 14 (Filtered)-I2S direction: (FDAC, FDAF, SDA); O FRESET 15 reset signal for SAA2521 O FSYNC 16 Filtered-I2S sync signal for SAA2521 O FDAF 17 Filtered-I2S sub-band filter data; 4 mA, 3-state output + CMOS input with pull-down I/O FDAC 18 Filtered-I2S sub-band codec data; 4 mA, 3-state output + CMOS input with pull-down I/O SCL 19 I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O SWS 20 I2S-word select; 4 mA, 3-state output + CMOS input with pull-down I/O SDA 21 I2S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down I/O PWRDWN 22 power-down mode; CMOS level I DSC4 23 test pin DSC3 24 test pin DSC2 25 test pin DSC1 26 test pin DSC0 27 test pin VDD 28 positive supply voltage (+5 V) RESET 29 system reset; CMOS level with pull-down and hysteresis I T1 30 test pin; do not connect T0 31 test pin; do not connect LTDATA 32 LT interface data; 4 mA, 3-state output + CMOS input with pull-down I/O LTCLK 33 LT interface bit clock; CMOS level I |
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