XRK4993

5

REV. 1.0.0

3.3V PROGRAMMABLE SKEW CLOCK BUFFER

In the PLL_BYPASS mode the PE input can be used to invert the outputs. Thus, for a 20% (High) duty cycle

input, all outputs will retain the 20% high condition with PE High. For PE Low, however, they will be 80% High.

PE does not effect the duty cycle of the divided outputs.

SPECIAL FUNCTIONS

The following special functions have been implemented in the chip.

PE pin:

aligned to the Feedback). PE=Low, aligns the FB_IN faliing edge to the CLKIN falling edge. PE=High, aligns rising

edges.

condition in a low-noise state.

OE pin:

keep frequency lock. OE is kept low to enable the outputs and High to disable them. This is a synchronized operation to

prevent "partial" clocks When OE goes high, the outputs will go to their disabled level at the end of the next active clock

cycle. The level is determined by the state of PE. If PE is high, the output will go low at the end of the cycle and remain

there until OE return to a low state. If PE is low, at the end of the next clock high state it will continue to remain high until

OE returns low.

this mode, taking both SEL(x)1 & 0 to the Low state will disable that bank's outputs.

Mid

Low or Mid

52nS

High

29nS

High

Low or Mid

12nS

High

10nS

(N/A)

LM

LL

LH

LM

(N/A)

LH

ML

ML

(N/A)

MM

MM

MH

(N/A)

HL

MH

HM

(N/A)

HH

HL

(N/A)

HM

(N/A)

LL/HH

DIVIDED

SELA[1:0]

SELB[1:0]

SELC[1:0]

FB_IN

CLKIN