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XRT83SL314IB Datasheet(PDF) 4 Page - Exar Corporation

Part # XRT83SL314IB
Description  14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT83SL314IB Datasheet(HTML) 4 Page - Exar Corporation

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XRT83SL314
xr
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS .......................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL314.................................................................................................................................. 1
FEATURES
..................................................................................................................................................................... 2
PRODUCT ORDERING INFORMATION ..................................................................................................2
PIN OUT OF THE XRT83SL314 ..................................................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS BY FUNCTION ............................................................................................. 4
MICROPROCESSOR ........................................................................................................................................................ 4
RECEIVER SECTION ....................................................................................................................................................... 5
TRANSMITTER SECTION.................................................................................................................................................. 8
CONTROL FUNCTION.................................................................................................................................................... 10
CLOCK SECTION .......................................................................................................................................................... 10
POWER AND GROUND .................................................................................................................................................. 11
NO CONNECTS ............................................................................................................................................................ 13
1.0 CLOCK SYNTHESIZER .......................................................................................................................14
TABLE 1: INPUT CLOCK SOURCE SELECT .............................................................................................................................................. 14
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER................................................................................................... 15
1.1 ALL T1/E1 MODE ........................................................................................................................................... 15
2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................15
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 15
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 16
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 16
TABLE 2: SELECTING THE INTERNAL IMPEDANCE.................................................................................................................................... 16
FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 16
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 17
TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 17
FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR.............................................................................. 17
2.2 EQUALIZER CONTROL ................................................................................................................................. 18
FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER AND PEAK DETECTOR ................................................................................. 18
2.3 CABLE LOSS INDICATOR ............................................................................................................................. 18
FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE CABLE LOSS INDICATOR................................................................................................ 18
2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 19
FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER ATTENUATION FLAG .................................................................................... 19
2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 19
TABLE 4: SELECTING THE SLICER LEVEL FOR THE PEAK DETECTOR....................................................................................................... 19
2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 20
FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 20
FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................. 20
TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG.................................................................................................................21
2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 21
FIGURE 11. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 21
2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 22
FIGURE 12. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 22
2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 22
FIGURE 13. INTERRUPT GENERATION PROCESS BLOCK ......................................................................................................................... 22
2.6.3.1 RLOS (RECEIVER LOSS OF SIGNAL) ..................................................................................................................... 22
FIGURE 14. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 23
TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 23
2.6.3.2 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 23
2.6.3.3 AIS (ALARM INDICATION SIGNAL) ......................................................................................................................... 23
2.6.3.4 NLCD (NETWORK LOOP CODE DETECTION) .......................................................................................................... 24
FIGURE 15. PROCESS BLOCK FOR AUTOMATIC LOOP CODE DETECTION ................................................................................................ 24
2.6.3.5 FLSD (FIFO LIMIT STATUS DETECTION) ............................................................................................................... 25
2.6.3.6 LCVD (LINE CODE VIOLATION DETECTION) ........................................................................................................... 25
2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 25
2.8 HDB3/B8ZS DECODER .................................................................................................................................. 25
2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 26
FIGURE 16. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 26
FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 26


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