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XRT86SH221 Datasheet(PDF) 9 Page - Exar Corporation |
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XRT86SH221 Datasheet(HTML) 9 Page - Exar Corporation |
9 / 353 page PRELIMINARY XRT86SH221 VI REV. P1.0.5 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU TABLE 183: TRANSMIT STM-0 PATH CURRENT POINTER BYTE REGISTER - BYTE 1 (TPCPR1 0X07C6) ........................................ 211 TABLE 184: TRANSMIT STM-0 PATH CURRENT POINTER BYTE REGISTER - BYTE 0 (TPCPR0 0X07C7) ........................................ 211 TABLE 185: TRANSMIT STM-0 PATH HP-RDI CONTROL REGISTER - BYTE 2 (TPHP-RDICR2 0X07C9) ........................................ 212 TABLE 186: TRANSMIT STM-0 PATH HP-RDI CONTROL REGISTER - BYTE 1 (TPHP-RDICR1 0X07CA) ....................................... 213 TABLE 187: TRANSMIT STM-0 PATH HP-RDI CONTROL REGISTER - BYTE 0 (TPHP-RDICR0 0X07CB) ....................................... 214 TABLE 188: TRANSMIT STM-0 PATH SERIAL PORT CONTROL REGISTER (TPSPCR 0X07CF) ....................................................... 214 6.8 GLOBAL E1 LINE INTERFACE UNIT REGISTER DESCRIPTIONS (LIU) .................................................... 215 TABLE 189: GLOBAL LINE INTERFACE CONTROL REGISTER 5 (GLICR5 0X0100H) ........................................................................ 215 TABLE 190: GLOBAL LINE INTERFACE CONTROL REGISTER 4 (GLICR4 0X0101H) ......................................................................... 216 TABLE 191: GLOBAL LINE INTERFACE CONTROL REGISTER 3 (GLICR3 0X0102H) ......................................................................... 216 TABLE 192: GLOBAL LINE INTERFACE CONTROL REGISTER 2 (GLICR2 0X0103H) ......................................................................... 217 TABLE 193: GLOBAL LINE INTERFACE CONTROL REGISTER 1 (GLICR1 0X0104H) ......................................................................... 217 TABLE 194: GLOBAL LINE INTERFACE CONTROL REGISTER 0 (GLICR0 0X0105H) ......................................................................... 217 6.9 INDIVIDUAL CHANNEL E1 LINE INTERFACE UNIT REGISTER DESCRIPTIONS (LIU) ............................ 218 TABLE 195: CHANNEL LINE INTERFACE CONTROL REGISTER 9 (CLICR9 0XN000H) ...................................................................... 218 TABLE 196: CHANNEL LINE INTERFACE CONTROL REGISTER 8 (CLICR8 0XN001H) ...................................................................... 219 TABLE 197: CHANNEL LINE INTERFACE CONTROL REGISTER 7 (CLICR7 0XN002H) ...................................................................... 220 TABLE 198: CHANNEL LINE INTERFACE CONTROL REGISTER 6 (CLICR6 0XN003H) ...................................................................... 221 TABLE 199: CHANNEL LINE INTERFACE CONTROL REGISTER 5 (CLICR5 0XN004H) ...................................................................... 222 TABLE 200: CHANNEL LINE INTERFACE CONTROL REGISTER 4 (CLICR4 0XN005H) ...................................................................... 223 TABLE 201: CHANNEL LINE INTERFACE CONTROL REGISTER 3 (CLICR3 0XN006H) ...................................................................... 224 TABLE 202: CHANNEL LINE INTERFACE CONTROL REGISTER 2 (CLICR2 0XN007H) ...................................................................... 225 TABLE 203: CHANNEL LINE INTERFACE CONTROL REGISTER 1 (CLICR1 0XN010H) ...................................................................... 226 TABLE 204: CHANNEL LINE INTERFACE CONTROL REGISTER 0 (CLICR0 0XN011H) ...................................................................... 226 6.10 E1 SYNCHRONIZATION FRAMER REGISTER DESCRIPTIONS (EGRESS DIRECTION ONLY) ............. 228 TABLE 205: CLOCK SELECT REGISTER (CSR 0XN100H) .............................................................................................................. 228 TABLE 206: SLIP BUFFER CONTROL REGISTER (SBCR 0XN116H) ................................................................................................ 229 TABLE 207: FIFO LATENCY REGISTER (FIFOLR 0XN117H) ......................................................................................................... 229 TABLE 208: FRAMING SELECT REGISTER RE-SYNC (FSRRS 0XN10BH) ....................................................................................... 230 TABLE 209: BLOCK INTERRUPT STATUS REGISTER (BISR 0XNB00H) ........................................................................................... 231 TABLE 210: BLOCK INTERRUPT ENABLE REGISTER (BIER 0XNB01H) ........................................................................................... 231 TABLE 211: ALARM AND ERROR STATUS REGISTER (AESR 0XNB02H) ......................................................................................... 232 TABLE 212: ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER 0XNB03H) ...................................................................... 232 TABLE 213: FRAMER INTERRUPT STATUS REGISTER (FISR 0XNB04H) ......................................................................................... 233 TABLE 214: FRAMER INTERRUPT ENABLE REGISTER (FIER 0XNB05H) ......................................................................................... 234 TABLE 215: SLIP BUFFER STATUS REGISTER (SBSR 0XNB08H) .................................................................................................. 235 TABLE 216: SLIP BUFFER INTERRUPT ENABLE REGISTER (SBIER 0XNB09H) ................................................................................ 235 6.11 VT MAPPING OPERATION CONTROL REGISTER DESCRIPTIONS......................................................... 236 TABLE 217: GLOBAL VT-MAPPER BLOCK - VT MAPPER BLOCK CONTROL REGISTER (VTMCR = 0X0C03) .................................... 236 TABLE 218: GLOBAL VT MAPPER BLOCK - TEST PATTERN CONTROL REGISTER 1 (VTMTPCR1 = 0X0C0E) ................................. 237 TABLE 219: GLOBAL VT-MAPPER BLOCK - TEST PATTERN CONTROL REGISTER 0 (VTMTPCR0 = 0X0C0F) ................................. 238 TABLE 220: GLOBAL VT-DEMAPPER BLOCK - TEST PATTERN DROP REGISTER 1 (VTDTPDR1 = 0X0C12) ................................... 239 TABLE 221: GLOBAL VT-DEMAPPER BLOCK - TEST PATTERN DROP REGISTER 0 (VTDTPDR0 = 0X0C13) ................................... 241 TABLE 222: GLOBAL VT-DEMAPPER - TEST PATTERN DETECTOR ERROR COUNT REGISTER 1 (VTDTPDECR1 = 0X0C16) .......... 243 TABLE 223: GLOBAL VT-DEMAPPER - TEST PATTERN DETECTOR ERROR COUNT REGISTER 0 (VTDTPDECR0 = 0X0C17) .......... 243 TABLE 224: GLOBAL VT-MAPPER - TRANSMIT TRIBUTARY SIZE SELECT REGISTER 1 (VTMTTSSR1 = 0X0C1A) ........................... 244 TABLE 225: GLOBAL VT-MAPPER - TRANSMIT TRIBUTARY SIZE SELECT REGISTER 0 (VTMTTSSR0 = 0X0C1B) ........................... 246 TABLE 226: GLOBAL VT-DEMAPPER - RECEIVE TRIBUTARY SIZE SELECT REGISTER 1 (VTDRTSSR1 = 0X0C1E) ........................ 248 TABLE 227: GLOBAL VT-DEMAPPER - RECEIVE TRIBUTARY SIZE SELECT REGISTER 0 (VTDRTSSR0 = 0X0C1F) ......................... 249 TABLE 228: CHANNEL CONTROL - VT-MAPPER E1 INSERTION CONTROL REGISTER 1 (VTME1ICR1 = 0XND42) ........................... 251 TABLE 229: CHANNEL CONTROL - VT-MAPPER E1 INSERTION CONTROL REGISTER 0 (VTME1ICR0 = 0XND43) ........................... 253 TABLE 230: CHANNEL CONTROL - VT-DEMAPPER E1 DROP CONTROL REGISTER 3 (VTDE1DCR3 = 0XND44) ............................ 255 TABLE 231: CHANNEL CONTROL - VT-DEMAPPER E1 DROP CONTROL REGISTER 2 (VTDE1DCR2 = 0XND45) ............................ 255 TABLE 232: CHANNEL CONTROL - VT-DEMAPPER E1 DROP CONTROL REGISTER 1 (VTDE1DCR1 = 0XND46) ............................ 256 TABLE 233: CHANNEL CONTROL - VT-DEMAPPER E1 DROP CONTROL REGISTER 0 (VTDE1DCR0 = 0XND47) ............................ 257 TABLE 234: CHANNEL CONTROL - VT-DEMAPPER BIP-2 ERROR COUNT REGISTER 1 (VTDBIP2ECR1 = 0XND4A) ...................... 260 TABLE 235: CHANNEL CONTROL - VT-DEMAPPER BIP-2 ERROR COUNT REGISTER 0 (VTDBIP2ECR0 = 0XND4B) ...................... 260 TABLE 236: CHANNEL CONTROL - VT-DEMAPPER REI-V EVENT COUNT REGISTER 1 (VTDREIECR1 = 0XND4E) ........................ 261 TABLE 237: CHANNEL CONTROL - VT-DEMAPPER REI-V EVENT COUNT REGISTER 0 (VTDREIECR0 = 0XND4F) ........................ 261 TABLE 238: CHANNEL CONTROL - VT-DEMAPPER RECEIVE APS REGISTER 1 (VTDRAPSR1 = 0XND52) .................................... 262 TABLE 239: CHANNEL CONTROL - VT-DEMAPPER RECEIVE APS REGISTER 0 (VTDRAPSR0 = 0XND53) .................................... 264 TABLE 240: CHANNEL CONTROL - VT-MAPPER TRANSMIT APS REGISTER 1 (VTMTAPSR1 = 0XND56) ....................................... 266 TABLE 241: CHANNEL CONTROL - VT-MAPPER TRANSMIT APS/K4 REGISTER 0 (VTMTAPSR0 = 0XND57) ................................. 267 TABLE 242: CHANNEL CONTROL - VT-DEMAPPER TANDEM CONNECTION - RECEIVE BIP-2 ERROR COUNT REGISTER 2 (VTDTCBIP2ECR = 0XND59) ................................................................................................................................................................. 267 TABLE 243: CHANNEL CONTROL - VT-DEMAPPER TANDEM CONNECTION - RECEIVE REI-V EVENT COUNT REGISTER 1 (VTDTCREIECR |
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