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XRT86SH221IB Datasheet(PDF) 11 Page - Exar Corporation |
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XRT86SH221IB Datasheet(HTML) 11 Page - Exar Corporation |
11 / 353 page PRELIMINARY XRT86SH221 VIII REV. P1.0.5 SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU 8.1 STM-0/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION .......................................................... 317 8.2 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS ............... 317 FIGURE 63. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE (FOR STM-0 APPLICATIONS) ...................................................................................................................... 317 TABLE 284 TIMING INFORMATION FOR THE TRANSMIT STM-0 TELECOM BUS INTERFACE - STM-0 APPLICATIONS ........................... 318 8.3 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT MASTER APPLICATIONS 318 FIGURE 64. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE (FOR STM-1 APPLICATIONS) ...................................................................................................................... 318 FIGURE 65. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP_IN_OUT OUTPUT PIN, AND THE TXA_CLK OUTPUT PIN , WITHIN THE TRANSMIT STM-1 TELECOM BUS INTERFACE (SLOT MASTER MODE APPLICATION) ............................... 319 TABLE 285 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 SLOT MASTER APPLICATIONS 319 8.4 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT SLAVE APPLICATIONS 320 FIGURE 66. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE OUTPUT VIA THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE (FOR STM-1 APPLICATIONS) ...................................................................................................................... 320 FIGURE 67. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP INPUT PIN AND THE TXA_CLK OUTPUT PIN WITHIN THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE (STM-1 SLOT SLAVE APPLICATIONS) ........................................... 320 TABLE 286 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 SLOT SLAVE APPLICATIONS 321 8.5 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS.................. 321 FIGURE 68. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE RECEIVE STM-0/STM-1 TELECOM BUS IN- TERFACE ..................................................................................................................................................................... 321 TABLE 287 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE - STM-0 APPLICATIONS ................. 321 8.6 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 APPLICATIONS.................. 322 FIGURE 69. AN ILLUSTRATION OF THE WAVEFORMS OF THE SIGNALS THAT ARE INPUT VIA THE RECEIVE STM-0/STM-1 TELECOM BUS IN- TERFACE ..................................................................................................................................................................... 322 TABLE 288 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE - STM-1 APPLICATIONS ................. 322 8.7 STM-0 LIU INTERFACE TIMING INFORMATION .......................................................................................... 323 8.7.1 RECEIVE STM-0/STM-1 LIU INTERFACE TIMING.................................................................................................... 323 FIGURE 70. AN ILLUSTRATION OF THE WAVEFORMS OF THE RECEIVE STM-0/STM-1 SIGNALS THAT ARE INPUT TO THE RECEIVE STM-0/ STM-1 LIU INTERFACE BLOCK - SHARED PORT ........................................................................................................... 323 TABLE 289 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 LIU INTERFACE WHEN THE RECEIVE STM-0/STM-1 TOH PROCESSOR BLOCK HAS BEEN CONFIGURED TO SAMPLE THE RXSTM0DATA SIGNAL UPON THE RISING EDGE OF THE RXSTM0CLK SIGNAL 323 8.7.2 TRANSMIT STM-0/STM-1 LIU INTERFACE TIMING................................................................................................. 324 FIGURE 71. AN ILLUSTRATION OF THE WAVEFORMS OF THE STM-0/STM-1 SIGNALS THAT ARE OUTPUT FROM THE TRANSMIT STM-0/STM- 1 LIU INTERFACE - DEDICATED PORT........................................................................................................................... 324 TABLE 290 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 LIU INTERFACE WHEN THE TRANSMIT STM-0/STM-1 TOH PROCES- SOR BLOCK HAS BEEN CONFIGURED TO UPDATE THE TXSTM0DATA SIGNAL UPON THE RISING EDGE OF THE TXSTM0CLK SIGNAL 324 8.8 TRANSMIT STM-0/STM-1 TOH AND POH DATA INPUT PORT ................................................................... 325 FIGURE 72. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT STM-0/STM-1 TOH AND POH OVERHEAD DATA INPUT PORT 325 TABLE 291 TIMING INFORMATION FOR THE TRANSMIT STM-0/STM-1 TOH AND POH OVERHEAD DATA INPUT PORT ..................... 325 8.9 TRANSMIT VC-4 POH DATA INPUT PORT ................................................................................................... 326 FIGURE 73. ILLUSTRATION OF TIMING WAVE-FORM OF THE TRANSMIT VC-4 POH DATA INPUT PORT ............................................. 326 TABLE 292 TIMING INFORMATION FOR THE TRANSMIT VC-4 POH DATA INPUT PORT ..................................................................... 326 8.10 RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT ................................................................ 327 FIGURE 74. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT...... 327 TABLE 293 TIMING INFORMATION FOR THE RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT ..................................... 327 8.11 RECEIVE VC-4 POH DATA OUTPUT PORT ................................................................................................ 328 FIGURE 75. ILLUSTRATION OF THE TIMING WAVE-FORM OF THE RECEIVE VC-4 POH DATA OUTPUT PORT..................................... 328 TABLE 294 TIMING INFORMATION FOR THE RECEIVE VC-4 POH DATA OUTPUT PORT ................................................................... 328 8.12 INGRESS DIRECTION - ADD/DROP PORT TIMING.................................................................................... 329 8.12.1 INGRESS DIRECTION - ADD PORT TIMING .......................................................................................................... 329 FIGURE 76. ILLUSTRATION OF THE INGRESS-DIRECTION ADD PORT SIGNALS ................................................................................ 329 TABLE 295 TIMING INFORMATION FOR THE INGRESS-DIRECTION ADD PORT SIGNALS ..................................................................... 329 8.12.2 INGRESS DIRECTION - DROP PORT TIMING........................................................................................................ 330 FIGURE 77. ILLUSTRATION OF THE INGRESS-DIRECTION DROP PORT SIGNALS ............................................................................... 330 TABLE 296 TIMING INFORMATION FOR THE INGRESS-DIRECTION DROP PORT SIGNALS ................................................................... 330 8.13 EGRESS DIRECTION - ADD/DROP PORT TIMING..................................................................................... 331 8.13.1 EGRESS DIRECTION - ADD PORT TIMING............................................................................................................ 331 FIGURE 78. ILLUSTRATION OF THE EGRESS-DIRECTION ADD PORT SIGNALS ................................................................................. 331 TABLE 297 TIMING INFORMATION FOR THE EGRESS-DIRECTION ADD PORT SIGNALS ...................................................................... 331 8.13.2 EGRESS DIRECTION - DROP PORT TIMING ......................................................................................................... 332 |
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