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XRK32308IDTR-4 Datasheet(PDF) 3 Page - Exar Corporation |
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XRK32308IDTR-4 Datasheet(HTML) 3 Page - Exar Corporation |
3 / 16 page PRELIMINARY XRK32308 3 REV. P1.0.3 3.3V ZERO DELAY BUFFER NOTES: 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the XRK32308–2. ZERO DELAY AND SKEW CONTROL To close the feedback loop of the XRK32308, the FB pin can be driven from any of the eight available output pins. The output driving the FB pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. TABLE 3: AVAILABLE XRK32308 CONFIGURATIONS DEVICE FEEDBACK FROM BANK A FREQUENCY BANK B FREQUENCY XRK32308-1 Bank A or Bank B Reference Reference XRK32308-1H Bank A or Bank B Reference Reference XRK32308-2 Bank A Reference Reference/2 XRK32308-2 Bank B 2 X Reference Reference XRK32308-3 Bank A 2 X Reference Reference or Reference[5] XRK32308-3 Bank B 4 X Reference 2 X Reference XRK32308-4 Bank A or Bank B 2 X Reference 2 X Reference XRK32308-5H Bank A or Bank B Reference/2 Reference/2 FIGURE 2. REF INPUT TO QAX/QBX DELAY VS DIFFERENCE IN LOADING BETWEEN FB AND QAX/QBX PINS 0 500 1000 1500 -500 -1000 -1500 Output Load Difference: FB Load - QAx/QBx Load (pF) -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 Note: Target only, actual characterization curve may be slightly different. |
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Similar Description - XRK32308IDTR-4 |
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